A Novel Rad-Hard Overlapping Circular-Gate Transistor and its Application to Analog Circuits

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Ricardo Vilaverde Graça
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1 CTI - IC Design House Brazil A Novel Rad-Hard Overlapping Circular-Gate Transistor and its Application to Analog Circuits Jader A. De Lima Center for Technology of Information (CTI), IC Design House Campinas-SP, Brazil

2 Outline I. Motivation II. Conventional Circular Gate Transistor (CGT) III. Overlapping Circular Gate Transistor (O-CGT) IV. Simulation Strategy and Results V. Application to Power-FETs VI. Application to Analog Design (OTA) VII. VTH Stabilization Techniques VIII. Conclusion

3 I. Motivation Circular-Gate Transistor (CGT) features: 1. minimal stray capacitance (high-frequency) 2. Higher BVDS due to smooth junctions contours 3. Enclosed-Layout Transistor (ELT) radiation hardened However 4. low layout compactness 5. no degree of freedom on choosing (W/L) 6. Large arrays are not area-effective with respect to rectangulargate structures 7. Not applicable to low R DSON power-fet implementation

Enclosed-Layout Transistor (ELT) radiation hardened However 4. low layout compactness 5.

4 LOCOS isolation (commonly used for commercial devices) Rectangular-Gate Transistor (RGT) edge leakage decreases efficiency on high-current DC/DC switchers positive charge trapping increases with radiation exposition ELTs (Enclosed Layout Transistors) show no bird s beak region

on high-current DC/DC switchers positive charge trapping increases

5 (a) illustrates LOCOS isolation commonly used for commercial CMOS technologies. (b) shows a traditional hardened field-oxide isolation. (c) Illustrates shallow-trench isolation used in deep submicron technologies. Shaneyfel et al. Challenges in Hardening Technologies Using Shallow-Trench Isolation, IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 45, NO. 6, DECEMBER 1998

(c) Illustrates shallow-trench isolation used in deep submicron technologies.

6 Rad-Hard By Layout (RHBL)

8 Active-region-cutout (ARC) technique: a small part of active short area is removed.

9 ELT with guard rings

10 2-channel DC/DC switcher (5A) Power FET (100mΩ) Power FET (100mΩ)

11 waffle transistors

12 HEXFET - International Rectifiers Patent (1979)

13 - US (Ming-Dou Ker et al 17 Nov 1998) (Hexagonal geometries)

II. Conventional CGT Source Gate Source Gate-oxide L V D V S Gate a mask b mask V G b msk Drain a msk Source N+ Drain N+ Source N+ L=b msk - a msk Source Source P-Substrate (a) V Subs (b) Figure 1.

14 II. Conventional CGT Source Gate Source Gate-oxide L V D V S Gate a mask b mask V G b msk Drain a msk Source N+ Drain N+ Source N+ L=b msk - a msk Source Source P-Substrate (a) V Subs (b) Figure 1. Simplified top-view layout of a conventional CGT (a) and its cross-section (b). I DS 2π = b ln a msk msk µ C ox V GS V TH V 2 DS V DS W L eff = 2π b ln a msk msk De Lima, J. A. - "Effective Aspect-Ratio and Gate-Capacitance in Circular Geometry MOS Transistors", Solid-State Electronics, Oct 1996.

Simplified top-view layout of a conventional CGT (a) and its cross-section (b).

15 Drain contact L Source contact L Drain contacts III. O-CGT O Structure Source contacts Source contact 2x2 array of O-CGT De Lima, J. A. and Gimenez, S. P. A Novel Overlapping Circular-Gate Transistor and its Application to Power MOSFETs, Electrochemical Society Transactions, Vol. 23, pp , 2009.

16 360 o 4θ 2π W = 360 o bmsk L eff,unity ln a msk 360 o 2θ 2π W = L 360 o bmsk eff,pair ln a msk

17 ATLAS3D simulation (W/L)eff error < 4.7%

18 Breakdown Voltage (BV DS )

19 Fabrication Process #1 V. Power-FET Layout a msk = µm b msk = 1.33 µm α = 27 o (W/L) eff = 8.8 Reduction of 18.36%

20 Fabrication Process #2 (W/L) eff = 16.1 matrix of 11x11 elements CASE A: dropout: 100mV I LOAD = 5mA R ON : 20Ω

21 detail

22 RGT = 2949µm 2 O-CGT = 1339µm 2 (55% area reduction) R ON : 20Ω

23 (W/L) eff = 16.1 CASE B: I LOAD = 2A R ON < 10mΩ 50 x50 elements implemented as 11 x 11 matrices of 50 x 50 elements each RGT = 1460um x 4100um = 0.59mm 2 O-CGT= um x um = 0.39mm 2 (61% area reduction) unity matrix

24 11 11 R ON < 10mΩ between sub-matrices: i)metal interconnection of gates (reduce RC and switching time) ii)substrate bias

25 VI. O-CGT O Applied to Analog Design - OTA Layout

26 OTA differential-pair layout with O-CGT (details)

27 VII. VTH Dynamic Adjustment Kerns et al - Threshold Voltage Stabilization in Radiation Environments, IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 45, NO. 6, DEC 1998

28 C1 = 30pF C2 = 50pF C1 = 30nF C2 = 50nF

29 VIII Conclusion An innovative rad-hard structure: O-CGT higher effective (W/L) than RGT A first-order model for the effective (W/L) of O-CGT was developed and its accuracy confirmed to a good degree, based on ATLAS3D sim (error < 4.7%) Simulated O-CGT BV DS is 6.46V; lower than RGT (6.60V) or CGT (6.88V) O-CGT can advantageously by used in power-fet layout Fabrication on progress (MOSIS/AMI) Dynamic adjustment of VTH should be further explored

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