Efeitos da Radiação em Circuitos Integrados Analógicos: Técnicas de Simulação e Hardening. Prof. Gilson I Wirth Eng.

Transcrição

1 Efeitos da Radiação em Circuitos Integrados Analógicos: Técnicas de Simulação e Hardening. Eng. Elétrica - UFRGS 28 de Outubro de

2 Radiation Effects in Analog Circuits Outline Basic Physical Mechanism Total Ionizing Dose () Displacement Damage Single Event Effects (SEEs) Hardening Techniques Simulation Techniques Efeitos da radiação em circuito integrados analógicos: técnicas de simulação e "hardening. 2

3 Ionization from Different Radiation Traceable to the energy deposition initiated by one single particle, in a precise instant in time. Due to its stochastic nature, this can happen at any time. Photon (X, γ) i Heavy Ion Proton p p Neutron n n h Silicon e Small density of e-h pairs h h e e h e h e h h e e h h e h e e h h e h h e h e e ee e h h h h h h h h h e e e e h hh e e h h e e e e Large density of e-h pairs p he ie h e h he e h e h h h h h h e e e e e e n Nuclear interaction p e h he i e h he e h e Small (proton) or negligible (neutron) density for direct ionization. Possible high density from Heavy Ion produced from nuclear interaction of the particle with Silicon nucleus. n Efeitos da radiação em circuito integrados analógicos: técnicas de simulação e "hardening. 3

4 Basic Physical Mechanisms Poly SiO 2 e h + V - h e + V - h h h h + V - h h h h + V - Si Oxide trapped charge ALWAYS POSITIVE! Interface states Can trap both e - and h + ( e - in NMOS and h + in PMOS) 4

5 Basic Physical Mechanisms - Ionizing radiation creates electron-hole pairs in the oxide. - Net positive charge trapped in the oxide changes potential in the Si. - Protons reaching the interface create interface traps: - Recombination centers - Electrostatic effects 5

6 Radiation Effects The Radiation Effects in Analog Circuits here Studied are Classified as: Total Ionizing Dose () Displacement Damage Single Event Effects (SEEs) Efeitos da radiação em circuito integrados analógicos: técnicas de simulação e "hardening. 6

8 Total Ionization Dose () Ionization in SiO 2 (protons, electrons, gammas, ) Creation of electron-hole pairs Buildup of charge/defects Device degradation Efeitos da radiação em circuito integrados analógicos: técnicas de simulação e "hardening. 8

9 Total Ionization Dose () The total ionizing dose (), mostly due to electrons and protons, can result in device failure (or biological damage to astronauts). In either case is measured in terms of the absorbed dose, which is a measure of the energy absorbed by matter. Absorbed dose is quantified using either a unit called the rad (an acronym for radiation absorbed dose) or the SI unit which is the gray (Gy); 1 Gy = 100 rads = 1 J/kg. It is material dependent, as the interaction between particles depend on atomic numbers, density and others. Efeitos da radiação em circuito integrados analógicos: técnicas de simulação e "hardening. 9

10 Source The is calculated from the trapped protons and electrons, secondary Bremsstrahlung photons, and solar flare protons (the contribution from galactic cosmic ray ions is negligible in the presence of these other sources). The main radiation dose is from solar energetic particle events (from solar flares), and passage through the South Atlantic Anomaly. In low earth orbit (LEO) the main dose source is from electrons and protons (inner belt), and In geostationary earth orbit (GEO) the primary source is from electrons and solar protons (outer belt). Efeitos da radiação em circuito integrados analógicos: técnicas de simulação e "hardening. 10

11 The total accumulated dose depends on orbit altitude, orientation, and time. To compute we need to know the integrated particle energy spectrum, (E), that is, fluence as a function of particle energy. Satellites and space probes typically encounter between 10 and 100 krad(si). Devices can be tested before use in laboratory facilities. In LEO, single event effects (SEE) are more of a problem although in 1991 bipolar devices were found to degrade worst from lower doses (< 0.1 rad/sec) in space than the higher values (e.g., rad/sec) used for laboratory tests. Many bipolar devices, most notably lateral PNP transistors, exhibit this enhanced low dose rate sensitivity (ELDRS). Efeitos da radiação em circuito integrados analógicos: técnicas de simulação e "hardening. 11

12 What does do? As increases, materials degradation increases, for example, solar cell output will decrease. Long-term exposure can cause device threshold shifts, increased device leakage and power consumption, timing changes, and decreased functionality. effects may be mitigated using radiation hardened devices and shielding. Electrons and low energy protons can be partially mitigated with shielding. Efeitos da radiação em circuito integrados analógicos: técnicas de simulação e "hardening. 12

13 Threshold for radiation effects Cumulative effects SEEs Integrated dose/fluence Danger Safe Particle energy Danger Safe 5-20MeV Low fluence = low occurrence rate BUT OCCURRENCE! Efeitos da radiação em circuito integrados analógicos: técnicas de simulação e "hardening. 13

14 Total Ionization Dose () Examples - Shielding is used for protection - sensitiveness depends on technology Efeitos da radiação em circuito integrados analógicos: técnicas de simulação e "hardening. 14

15 Analog Total Dose Effects 15

16 Total Dose Effects - Leakage current between devices or (source-todrain) emitter-to-collector: Major failure mechanism in digital bipolar ICs Can be avoided by process design or layout - Gain degradation: Serious problem for analog ICs Parametric or functional failures 16

17 MOS Transistor V G > n + n + 17

18 MOS Transistor Vg < 0 0<Vg < Vt Vg > Vt _ Silicio p Silicio p Silicio p Legenda: - Aceitador Ionizado - Elétron Livre + Lacuna (móvel) 18

19 MOS Transistor óxido de campo óxido de porta 19

20 MOS Transistor PMOS sem máscara NMOS 20

21 MOS Transistor 21

22 IC level leakage V DD POLYSILICON V SS OXIDE + + N+ WELL CONTACT N+ SOURCE N WELL LEAKAGE SUBSTRATE The charges trapped in the thick oxide (LOCOS or STI) decrease the Vth of the MOS structure, and the p substrate can be inverted even in the absence of an electric field. A leakage current can appear. 22

23 Chip Level Leakage: Field Oxide FETs 0.7 µm Technology 23

24 Chip Level Leakage: Field Oxide FETs 130nm Technology: STI PC or M1 gate 24

25 Chip Level Leakage: Power Dissipation 25

26 Transistor level leakage Parasitic MOS Parasitic channel Field oxide Trapped positive charge Bird s beak 26

27 Isolation-Related Leakage 27

28 Transistor Level Leakage Example: 0.18 um 28

29 Analog Total Dose Effects: MOSFETs Fixed Charge (trapped holes) affects mainly V T Interface states affect slope and V T 29

30 MOSFETs: Trapped holes = Positive charge 30

31 MOSFETs: Interface traps = Charge exchange 31

32 MOSFETs: Interface traps = Charge exchange 32

34 Analog Total Dose Effects: g m degradation 34

35 Analog Total Dose Effects: MOSFETs MOSFET:Degraded V T, Mobility and Sub-threshold leakage 35

36 Low-Frequency Noise in MOSFETS 1/f noise spectra of irradiated n-channel MOSFETS 36

37 Low-Frequency Noise in MOSFETS Gate Oxide Trap Inversion layer Drain Current I D Interaction with the inversion layer 37

38 Noise Spectra Produced by Interface States Source of the LF-noise of MOSFETs are trap-states at the Si/SiO 2 interface which are randomly charged and discharged in time Leads to modulation of the local mobility and number of free carriers in the channel Probability of a trap state to switch is occupation level depends on the energetic position of the local Fermi level 38

39 Noise Spectra Produced by Interface States S(log) Current τc διd τe Time f(log) 39

40 1/f-Noise of Large Area MOSFETs S(f) f(hz) Corner frequencies approximately uniformly distributed on a log scale 40

41 1/f-Noise of Small Area MOSFETs Gate referred voltage noise [VHz -1/2 ] 10-3 n-mos, W / L = 0.25µm / 0.25µm V d = 1.0V, V g,eff = 0.5V Frequency [Hz] Strong fluctuations in the LF-noise in small area devices 41

42 effects and t ox scaling Damage decreases with decreasing gate oxide thickness. Leakage between devices may still be a problem. 42

43 in CMOS: Summary of the problems Main transistor: Threshold voltage shift, transconductance and noise degradation: Effects get smaller in modern deep submicron (as from nm techs). Parasitic leakage paths: Source drain leakage Leakage between devices This are still potentially deleterious although things looks to be better as from 130nm techs In modern technologies, leakage current is typically the killer. 43

44 Chip Level Mitigation Ex.: Channel Stop Implants 44

45 Radiation-Induced Leakage Path 45

46 Radiation-Induced Leakage Path 46

47 Transistor Level Leakage Path Guard Ring 47

48 Function of the Guard Ring Guard Ring 48

49 Hardness By Design (HBD) Approach Work of: F. Faccio, CERN V DD GuardV Ring SS V SS OXIDE N+ DRAIN P+ GUARD N+ SOURCE SUBSTRATE p+ guardring G D S 49

50 Radiation Tolerant Approach (Layout) Guard Ring ELT + Guard Rings = Tolerance ELT = Enclosed Layout Transistor 50

51 Core NMOS, linear layout, 0.13um Work of: F. Faccio, CERN Wide transistors (W > 1µm): When the transistor is off or in the weak inversion regime: Leakage current appears (for all transistor sizes) Weak inversion curve is distorted Narrow transistors (W < 0.8µm): An apparent Vth shift (decrease) for narrow channel transistors The narrower the transistor, the larger the Vth shift (RINCE) Id (A) Foundry A, 2/ E-02 1.E-03 1.E-04 1.E-05 1.E-06 1.E-07 1.E-08 1.E-09 1.E Vg (V) Pre-rad 3Mrad 136Mrad 2d HT ann Id (A) 1.E-03 1.E-04 1.E-05 1.E-06 1.E-07 1.E-08 1.E-09 1.E-10 1.E-11 1.E-12 Foundry A, 0.16/ Vg (V) Pre-rad 3Mrad 136Mrad 2d HT ann 51

52 Core NMOS, linear layout, 0.13um Work of: F. Faccio, CERN E field lines STI Oxide trapped charge Polysilicon gate Depletion region STI Interface states 52

53 Core NMOS, ELT, 0.13um Work of: F. Faccio, CERN The radiation hardness of the gate oxide is such that practically no effect is observed verified for 2 foundries (A up to 140Mrad, B up to 30Mrad) NMOS ELT min/ E E-04 Foundry A, NMOS Id (A) 1.00E E E E E E E E Vg (V) Pre-rad 3Mrad 136Mrad 2d HT ann 53

54 Core PMOS, ELT, 0.13um Work of: F. Faccio, CERN The radiation hardness of the gate oxide is such that practically no effect is observed verified for 2 foundries (A up to 140Mrad, B up to 30Mrad) 1.E-03 PMOS ELT min/012 Foundry A, PMOS Id (A) 1.E-04 1.E-05 1.E-06 1.E-07 1.E-08 1.E-09 1.E-10 1.E-11 1.E Vg (V) pre-rad 3 Mrd 40 Mrd 54

55 Layout Example: Inverter Guard Ring 55

56 Effectiveness of ELT: 0.7um V T shift Guard Ring 56

57 Effectiveness of ELT: 0.25um no V T shift Guard Ring 57

58 Difficulties of ELT Guard Ring Peculiar ELT Behaviour: - Modeling of ELT (size W/L?) - Limitation in aspect ratio - Asymmetry of S-D Lack of commercial library for digital design Loss of density Yield and Reliability? 58

59 CERN Results Guard Ring 59

60 CERN Results: Drain Source Assimetry Guard Ring 60

61 CERN Results: Set of Cells Designed Guard Ring 61

62 CERN Results: Yield and Reliability Guard Ring 62

63 Total Dose Effects: Bipolar Transistors 63

64 Total Dose Effects: Bipolar Transistors 64

65 Total Dose Effects: NPN Transistors 65

66 Total Dose Effects: PNP Transistors 66

70 Efeitos da radiação em circuito integrados analógicos: técnicas de simulação e "hardening. 70

71 Displacement Damage 71

72 Displacement Damage and Electron Device Behavior Displacement damage is harmful in devices sensitive to bulk semiconductor properties, as it affects the minority carrier lifetime, the carrier mobility and the net doping level in the bulk material: Silicon-based detectors (such as microstrip detectors) for High Energy Physics applications Solar cells Optoelectronic devices (such as optocouplers) Bipolar devices (Not much on MOSFET): Gain degradation due to increased recombination of minority carriers in the base. Results on biased and unbiased devices are almost identical. Efeitos da radiação em circuito integrados analógicos: técnicas de simulação e "hardening. 72

73 Bipolar Technologies Leakage paths and β degradation Sensitive with dose rate effects Variable failure levels Simultaneous effects: they add up Displacement damage β degradation Voltage regulators, comparators, op amps Efeitos da radiação em circuito integrados analógicos: técnicas de simulação e "hardening. 73

74 Different evolution of defects - All charge trapped in the oxide or in the interface states affect the electric field across the oxide (hence the Vt of the structure). - The evolution of charge trapping and interface state formation during and after irradiation is different. This is very relevant for the overall evolution of the measured behavior. Example: very thick oxide NMOS V (V) Contrib from interface states Net effect on Vth Contrib from charge trapped in oxide E+04 1.E+05 1.E+06 1.E+07 1.E+08 (rd) - Annealing, or self-healing, is typically driven by thermal energy or hopping of carriers from the Si layer (only about 3nm range). It is normally effective for trapped charge only, not for interface states (exception recently pointed out for thick field oxides) 74

75 Different evolution of defects 75

76 Different evolution of defects 76

77 Implication for Testing/Qualification Accelerators Space Laboratory Weapons Test 1.E-06 1.E-03 1.E+00 1.E+03 1.E+06 1.E+09 1.E+12 Typical dose rate (rad(si)/s) 77

78 Bias and Radiation Type Dependence 78

79 Bias Dependence and Annealing: Example S u p p ly C u rren t (m A ) FPAAs Supply Current (ma) Total Dose (Krad) FPAA1 Post Post FPAA2 Degradation in the supply current under Co-60 irradiation. FPAA1: continuously powered. FPAA2: powered during 20% of irradiation time. 79

80 Example: LM117 Voltage Regulator Efeitos da radiação em circuito integrados analógicos: técnicas de simulação e "hardening. 80

81 Bias Dependence Bias condition during irradiation is VERY relevant for the radiation effects. During irradiation, the worst-case bias condition pushes holes towards the Si-SiOSiO 2 interface. Example: Vth shift of NMOS in 3 different bias conditions Vth (V) Vgs=Vdd Vgs=Vdd/2 Vgs=0V CMOS 130nm tech W/L=0.16/0.12um The larger the positive bias, the larger the Vth shift E+05 1.E+06 1.E+07 (rad) RULE: Power circuits in their operational condition, or a condition known to be worst-case! 81

82 Analog Total Dose Effects: Variability COTS Variability: OP27 Op-Amp 82

83 Different Manufacturers COTS: Same Part, Different Manufacturer 83

84 Analog Total Dose Effects: ELDR & Variability COTS / ELDR Part Variation: Same Manufacturer 84

85 Analog Total Dose Effects: ELDR & Variability COTS / ELDR Part Variation: Manufacturer Variation 85

86 Shielding Guard Ring -Electrons more effectively shielded than protons - Incremental shielding gives diminished returns 1 mil = mm 86

88 Analog Single-Event Transients Q9 Strike locations Simulation vs. laser for strikes on gain stage Simulation vs. microbeam for strike on input stage Q3-Input stage 88

89 Analog SET in 1.15GHz VCO (HCMOS7 0.25µm) 89

90 Simulation of : Leakage Sources 90

91 Simulation of : Change the Model Parameters *** PAREMETERS i-leak***.param b1=agauss(0,0.7,3) ***PARAMETERS VTh***.PARAM delta_vt1=agauss(0,0.6,3) **TRANSISTORES** M pmos L=1.2u W= 2.2u delvto=delta_vt1 ** SOLICITAÇÃO DE ANÁLISE**.ac dec SWEEP MONTE=1000 **SOLICITAÇÃO DE RESULTADOS**.PRINT ac vdb(6) vp(6) 91

92 Simulation of SET: Inject Transient Current I(t)(uA) Io=90uA, tf=100ps Io=140uA, tf=40ps Io=75uA, tf=150ps Io=105uA, tf=70ps ,2 0,4 0,6 0,8 1 time(ns) 92

93 Simulation of SET: Inject Transient Current Simulação elétrica (Spice) do pulso transiente pela dupla-exponencial; I 0 τ β τ α iexp 0 nodo exp(0 190u 1n 10p 1n 320p) *transição 0->1->0 iexp nodo 0 exp(0 190u 1n 10p 1n 300p) *transição 1->0->1 93

94 IEEE CASS School De 11 a 14 de Janeiro de 2010 Na UFRGS em Porto Alegre Foco em Confiabilidade, incluindo: Efeitos de Radiação NBTI Variabilidade / Matching Design for Manufacturability Palestrantes da: ASU, Vanderbilt, IBM, etc. 94