CMOS - Devices. Resistors

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Thalita Peres Laranjeira
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1 Resistors Z A W L sheet resistance If Z = cte, a square (L = W) has a resistance value which is independent of W : R = ρ L / A = ρ L / (W Z) = ρ / Z A rectangle has a resistance: R = ρ L / (W Z) = R L / W Ex: A 1 0, ,5 B R AB = ( 3 + 0,5 + 0,55 ) R

2 Mobility σ = q ( N ) D µ + N µ p n A

3 Resistivity of semiconductors σ = q ( N ) D µ + N µ p n A

Resistors Implementation of linear resistors: - With poly (+salicide block if available) - With diffusion (+salicide block if available) Depending on the PDK can be extracted as

4 Resistors Implementation of linear resistors: - With poly (+salicide block if available) - With diffusion (+salicide block if available) Depending on the PDK can be extracted as 2 or 3 terminal devices: Large resistor values require large areas (long devices) hence large parasitic capacitances may result. -Usually the main tradeoff consists on AREA x POWER

5 Resistors Due to the large Ω/sq values poly resistors (AND well) are very sensitive toward variations in L and W which results in fairly large tolerance levels (30% tolerance simulations are required). The absolute accuracy is quite poor. The relative match is much better.

6 Resistors Non-linear resistors or voltage dividers can be implemented with MOS transistors (1/2, 1/3, 2/3, ) V DD V DD / 2 The threshold voltage must be achieved in each transistor

7 Capacitors Capacity An overlap area A causes a capacitance C = A C x,, where C x represents the capacity density. kε A t C 0 = k = dielectric constant (SiO 2 = 3.9) ε o = 8.85 x F/m A = capacitor area (m 2 ) T = dielectric thickness (m)

8 Capacitors Metal Insulator Metal (MIM) MOSCAP POLY capacitors varactor

Capacitors Metal Insulator Metal (MIM): MIMCAP s require no analog-specific processing steps and are readily implemented in any IC process. Implements only relatively small capacitance values.

9 Capacitors Metal Insulator Metal (MIM): MIMCAP s require no analog-specific processing steps and are readily implemented in any IC process. Implements only relatively small capacitance values. A combination of large h and the resulting moderate inter-metal coubling the area efficiency is limited. Suffers from back-plate parasitic capacitance which makes their use limited in differential designs. The MIMCAP is a linear device with respect to voltage. Has relative small temperature dependency. - If more than two metal layers are available one would NEVER use the bottom two, unless the bottom plate effect is desired.

Capacitors MOSCAP: -MOS and MIMCAP s are close relatives. The only difference is that MOSCAP use gate oxide as isolator. Gate oxide is a key parameter and is tightly controlled.

10 Capacitors MOSCAP: -MOS and MIMCAP s are close relatives. The only difference is that MOSCAP use gate oxide as isolator. Gate oxide is a key parameter and is tightly controlled. This implies that h is small (equal to tox) resulting in fairly large and accurate capacitance values. - MOS (unlike MIM) requires contacts to access the N+ layer which adds parasitic resistors.

11 Capacitors MOSCAP: -When evaluated the C(Vg) characteristic reveals three distinctively different areas:

12 Capacitors POLY: -If available, double-poly capacitors represent a better solution if linear operation is desired. -Here two poly layers are available and these are used to form the two plates of the capacitor. -Parasitics are still present but as the two poly plates are very closely spaced the capacitance is dominated by the plate capacitance.

13 Capacitors POLY: -To limit parasitic resistance quite a few contacts have to be used to form the connections to the poly plates. To help minimize this effect a finger structure like that used for the MOSFET may be utilized for capacitors as well.

14 Capacitors Varactors: -Finely tunable capacitances are needed for different designs -MOSCAP C(V) -PN junction on nwell

15 Capacitors Junction capacity: C = A C j + P C jsw A represents the junction bottom area and C j is the capacitance density, P represents the junction perimeter C j and C jsw are spice parameters that depend on the junction voltage

16 Diodes Diodes are useful for: -voltage reference circuit design (bandgap) -voltage clamping Vdd Vss

17 Diodes Process limited connectivity: In a P substrate In a Nwell A B A B A B A p+ subs. p n+ p+ Vss p+ n+ poço n- p+ subs. p Vss

18 LATCH-UP

19 LATCH-UP CMOS - Devices

20 Parasitas Dispositivos parasitas formados durante o processo de fabrico Podem reduzir o desempenho ou até impedir o funcionamento Resistências parasitas: Todos os caminhos condutores do circuito têm uma resistência associada As resistências atrasam a propagação dos sinais É a razão da passagem do routing de Al para Cu Capacidades parasitas: Há capacidades parasitas entre cada dois níveis condutores sobrepostos e em cada junção PN Os condensadores atrasam a propagação dos sinais

21 EfeitosCMOS Parasitas - Devices (CMOS) Parasitas Lineares Não Lineares Interligações: capacidades: C poly, poly, C m1, m1, etc etc resistências: R poly, poly, R n+, n+, etc etc + indutâncias... TMOS: cap. cap. sobreposição (CGSO,CGDO,CGBO) Capacidades não não lineares de de junção (plana e curva) de de porta-canal Díodos de de Junção (junções n+/sub, p+/well) Transistores de de Junção Bipolar (hor., vert.) TMOS parasitas (fora das das áreas activas)

22 Parasitas Transístores parasitas: Formam-se pela alternância de junções PN (na vertical ou horizontal) A entrada em condução destes dispositivos é denominada Latch-Up Usados em alguns circuitos (ex: bandgap) substrate contact Drain Gate Source n-well contact p+ p+ p+ n+ n-well

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