OBS: A resolução de alguns exercícios está escrita à mão no fim da lista.

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1 Disciplina: ELD0001 Gabarito da lista de exercícios 1 Joinville, 20 de março de 2016 E11.1. Curso de engenharia elétrica Professor Renan Sebem mpound-gate #1 OBS: A resolução de alguns exercícios está escrita à mão no fim da lista. ite the equation for the function y implemented by each circuit of Figure E11.2 (note that one does contain an inverter 1. Escreva at the a equação output). para a função y implementada pelos circuitos (a) e (b) através de mosfets. E11.2. a) OBS: A ordem das entradas está diferente da ordem utilizada em sala de aula, mas o resultado é o mesmo! mpound-gate #2 Tabela verdade: aw the CMOS circuit Entradas for the following Saída functions: D C B A Y y = a + b c + d e f y = a (b + c) (d + e 0+ f ) Are there any similarities between 1 1the resulting circuits? mpound-gate # nsider the function 0 y = 1 a b 1 c. 0 1 Draw its CMOS 0 circuit 1 using 1 1 the SOP-based 0 procedure described in Section 11.4, Figure 11.3(a) Draw its CMOS 1circuit 0 using 0 1the POS-based 0 procedure described in Section 11.4, Figure 11.3(b). Draw it employing 1 the 0 equivalent 1 0 0equation y = (a + 0) (b + 0) (c + 0), and show that exactly the same circuit results 1 as 0 that 1 in 1part (a) 0 above Mapa de Karnaugh: Y B A B A B A B A D C D C D C D C Equação: Y = D B + D A + D C Y = D (A + B + C) Página 1 de 7

2 Disciplina: ELD0001 Gabarito da lista de exercícios 1 Joinville, 20 de março de 2016 b) Tabela verdade: Entradas Saída C B A Y Mapa de Karnaugh: Y B A B A B A B A C C Encoders and Decoders Equação: Y = A + B + C The circuit shown in Figure 11.8(b) is a direct implementation of the SOP expressions listed above ) is a direct implementation of the SOP expressions listed above using AND 2. gates. Escolha In afigure quantidade 11.8(c), dea entradas, CMOS architecture desenhe o símbolo is depicted, umwhich codificador was obtained e um decodificador, using the POS identificando CMOS architecture is depicted, which was obtained using the POS equations and as the entradas procedure e saídas. described in Section 11.4 (notice that some of the transistors are shared ed in Section 11.4 (notice that some of the transistors are shared between adjacent branches), thus resulting in a NOR gate in each column. In Figure 11.8(d), pseudonmos logic was employed instead of CMOS, again based on the POS expressions (so each column is ulting in a NOR 3. Suponha gate in que each umcolumn. chip de memória In Figure tem 11.8(d), capacidade pseudof CMOS, again (ou based sejaon the POS linhas). expressions Qual o valor (so each de N column (númerois de entradas para este decodificador? de 4 GB, dividida em 62,5 M palavras de 64 bits cada still a NOR gate). Finally, in Figure 11.8(e), footed dynamic logic was employed, and the implementation.8(e), footed dynamic logic was employed, and the implementation was based 4. on Projete the SOP e implemente, expressions através instead deof portas POS, lógicas, thus resulting um decodificador in NAND degates endereço in the 3/8columns conforme(in a tabela this abaixo: tead of POS, thus resulting in NAND gates in the columns (in this case, the dissimilar (a) Obtenha bit is low a espressão instead ótima of high). of high). para cada saída através do mapa de Karnaugh; (b) Implemente o circuito utilizando apenas portas NAND, e inversores se necessário. 283 with enable #2 xercise above, FIGURE but Sem without (a) Address modificar modifying decoder o circuito your symbols; do exercício solution (b) Truth 4, table adicione to Exercise for N = portas 11.9, 3, with lógicas introduce s indicated in Figure E11.11, to allow the inclusion of an output-enable the (ena) dissimilar a port, fim de bit criar equal uma to porta '1' ( one-hot de enable para o ols; ates code). (b) as Truth a regular table decodificador decoder for N = 3, with when como the ena dissimilar indica = '1', or a figura bit lowers equal abaixo. all to outputs '1' ( one-hot when ena = '0'. Resolvido em sala de aula with high-impedance output e address decoder of Figures E11.9 and E11.11, assume that now the enable rted, must turn the outputs into a high-impedance state (see tri-state buffers in Página 2 de 7

3 , must turn the outputs into a high-impedance state (see tri-state buffers in t u r n i n g t h e m l o w. I n c l u d e t h e a p p ro p r i a t e c i rc u i t f o r t h a t t o h a p p e n i n t h e stion mark in Figure E pseudo-nmos logic Disciplina: ELD0001 Gabarito da lista de exercícios 1 Joinville, 20 de março de 2016 ecoder of Figure E11.9, after obtaining the corresponding output equations, lementation using pseudo-nmos logic (as in Figure 11.8(d)). 6. Ainda utilizando o resultado do exercício 4, utilize buffers de terceiro estado para substituir o enable. more inputs #1Resolvido em sala de aula ss decoder using only 3-bit address decoders. 7. Construa um decodificador de 5 bits, utilizando apenas decodificadores de 3 bits com enable. Resolvido em sala de aula 266 CHAPTER 11 Combinational Logic Circuits 8. Para um codificador com N = 3: O circuito está anexado no fim da lista. more inputs #2 (a) Escreva a tabela verdade; (b) Escreva a expressão booleana ótima para cada saída; ss decoder using only 3-bit address decoders. (c) Desenhe o circuito. Tabela verdade: Entradas Saídas a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 y 2 y 1 y FIGURE Timing 0 0 diagram 1 0for a 02-bit 0 address 1 decoder implemented with conventional gates SOLUTION The solution is included in Figure Note that, to make it easier to follow, plots for x 1 and x were 1 also 0 included. 0 0 As 0 can 0 be observed, 1 0 1only one output is high at a time. However, depending on 0 1 the 0specific 0 0implementation and 1 its 1propagation 0 delays, glitches might occur during the transitions 1 0 (which 0 0are generally 0 0 0acceptable 0 1 in this 1 type 1 of circuit). Utilizando o mapa de Karnaugh as equações para y 2, y 1 e y 0 resultariam em 4 minitermos de 8 variáveis. Este circuito não é ótimo pois sabe-se que apenas uma das entradas estará ativa por vez. Conhecendo este fato é possível projetar Address o circuitoencoder para as saídas através de portas OR, utilizando nas entradas as variáveis que estão em nível lógico 1 quando a saída projetada está em nível lógico 1 : An address encoder does precisely the opposite of what an address decoder does, that is, it converts a y 2 = 2 a N 7 -bit + a 6 input + a 5 that + a 4 contains only one dissimilar bit into an N-bit output that encodes the position (address) y 1 = of a 7 the + a 6 dissimilar + a 3 + a 2 bit. Figure shows three equivalent address encoder symbols plus the truth table y 0 = for a 7 + N a= and a 3 + also a 1 an implementation example (for N = 2) using OR gates. Many other parallel encoders/decoders exist besides the address encoder/decoder. An example is 9. Projete given através below. de portas lógicas, um codificador de prioridade 2/4 conforme a tabela abaixo: Resolvido em laboratório x y FIGURE (a) Address encoder symbols; (b) Truth table for N = 2; (c) Implementation example with OR gates. EXAMPLE 11.4 SSD DECODER Figure 11.13(a) shows a seven-segment display (SSD), often used to display BCD-encoded numeric digits from 0 to 9 and also other characters. Two common technologies employed Página their 3fabrication de 7 are LEDs (light emitting diodes) and LCD (liquid crystal display). The segments have one end in common,

4 Disciplina: ELD0001 Gabarito da lista de exercícios 1 Joinville, 20 de março de Encoders 10. and Preencha Decoders a tabela e projete através de portas lógicas, um decodificador BCD/SSD (binary 267 coded decimal/ seven segment display): OBS: Escolha entre o display de cátodo comum ou ânodo comum. ders and Decoders Resolvido em laboratório 267 Entrada Saída Cátodo comum Saída Ânodo Comum GURE (a) Desenhe Seven-segment o circuito display de um multiplexador (SSD); (b) Common-cathode 4x1 utilizando somente configuration; portas NAND, (c) Common-anode e inversores se necessário. nfiguration; (d) BCD-to-SSD converter symbol; (e) Truth table for common-cathode decoder. Similar ao resolvido em laboratório.13. (a) Seven-segment display (SSD); (b) Common-cathode configuration; (c) Common-anode tion; normally (d) BCD-to-SSD 13. connected Desenhe converter to oground, circuito symbol; so dea um (e) segment demultiplexador Truth table is turned for common-cathode ON 1x4. when the bit decoder. feeding it is '1'. In the commonanode configuration, Resolvido the emanode laboratório is normally connected to V DD, so the opposite happens, that is, a segment connected is turned ON when its corresponding bit is '0' (inverted logic). In this example, we are interested in ally 14. to Construa ground, um so a multiplexador segment is turned 8x1 utilizando ON when apenas the bit multiplexadores feeding it is '1'. 4x1. In the commonconfiguration, using SSDs to the display anode the is output normally of a connected BCD counter to V(decimal digits from 0 to 9). Each digit is represented DD, so the opposite happens, that is, a segis turned by 4 bits, ON 15. while when Adicione an its SSD corresponding um requires buffer 7 de bits terceiro is to '0' drive (inverted estadoa digit nalogic). (or saída 8 if In dothe this multiplexador decimal example, point we a are fim is also interested de controlar used). Therefore, in a alta impedância na SSDs a BCD-to-SSD display porta the converter output de saída (also of a y. called BCD counter SSD driver (decimal or SSD digits decoder) from is 0 needed. to 9). Each A symbol digit is for represented such a converter display its, appears while (SSD); an in Figure SSD (b) Common-cathode requires 11.13(d), 7 bits and to the drive corresponding configuration; a digit (or truth 8 (c) if Common-anode the table, decimal for positive point is logic also (that used). is, Therefore, common-cathode) ter -to-ssd in symbol; Figure converter (e). Truth É possível (also Design table formar called for a SSD decoder common-cathode um decodificador driver to perform SSD decoder. a partir de um demultiplexador? Como? decoder) the BCD-to-SSD is needed. conversion. A symbol for Recall such that a converter Karnaugh maps rs can in Figure be helpful 11.13(d), to obtain and the an corresponding optimal (irreducible) truth table, SOP for positive POS expression logic (that for is, the common-cathode) segments (a, b,..., g). ure o a 11.13(e). segment Design is turned a decoder ON when to perform the bit feeding the BCD-to-SSD it is '1'. In the conversion. commonis helpful SOLUTION normally to obtain connected an optimal to V DD Recall that Karnaugh maps (irreducible), so the opposite SOP or happens, POS expression that is, a for segesponding The input bit bits is '0' are (inverted represented logic). by In this ABCD example, in the we truth are table, interested and the in output bits by abcdefg. For each the segments (a, b,..., g). t of TION output a BCD bit, counter a corresponding (decimal digits Karnaugh from 0 to 9). map Each is digit shown is represented in Figure 11.14, from which we obtain the nput 7 bits following bits to drive are equations: represented a digit (or 8 by if the ABCD decimal in the point truth is also table, used). and the Therefore, output bits by abcdefg. For each led t bit, SSD a = A a driver + corresponding or SSD decoder) C + B D + B D Karnaugh is needed. map A is symbol shown for in such Figure a converter 11.14, from which we obtain the e ing corresponding equations: truth table, for positive logic (that is, common-cathode) der b = to B perform + C D + the C BCD-to-SSD D conversion. Recall that Karnaugh maps C al + B D + B D c (irreducible) = (A C D SOP ) or POS expression for the segments (a, b,..., g). + C D + C D d = A + B C + B D + C D + B C D B C D ) by e ABCD = B D in + C the D truth table, and the output bits by abcdefg. For each B C + B D + C D + B C D arnaugh f = A + B map C B is D shown + C D in Figure 11.14, from which we obtain the D + C D g = A + B C + B C + C D B C + B D + C D An AND-OR implementation for each of these expressions is shown along with the Karnaugh B maps C + B in C Figure + C D Another implementation, using only NAND gates, is shown at the bottom of ND-OR Figure implementation for each of these expressions is shown along with the Karnaugh in Figure Another implementation, using only NAND gates, is shown at the bottom of D e Escolha a quantidade de entradas, desenhe o símbolo de um multiplexador e um demultiplexador, identificando as entradas e saídas. for each of these expressions is shown along with the Karnaugh implementation, using only NAND gates, is shown at the bottom of Página 4 de 7

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