Aula 3 - Famílias lógicas

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1 Aula 3 - Famílias lógicas Prof. Renan Sebem Disciplina de Eletrônica Digital Graduação em Engenharia Elétrica Universidade do Estado de Santa Catarina Joinville-SC Brasil 1 de março de 2016 ELD0001 Prof. Renan Sebem Aula 3 1 / 18

2 Conteúdo da Aula Famílias Lógicas Lógica TTL CMOS Formas de onda binárias Bibliografia ELD0001 Prof. Renan Sebem Aula 3 2 / 18

3 Famílias Lógicas Classificação Baseado em BJT (bipolar junction transistor): DTL (diode-transistor logic); TTL (transistor-transistor logic); ECL (emitter-coupled logic). Baseado em MOS (metal-oxide semiconductor): CMOS (complementary MOS); Pseudo-nMOS; Transmission-gate logic; BiCMOS; Dynamic MOS; Lógica Dominó; C 2 MOS. ELD0001 Prof. Renan Sebem Aula 3 3 / 18

4 Famílias Lógicas Exemplo - DTL 0.3 Transistor-Transistor Logic (TTL) 221 IGURE DL and DTL architectures: (a) DL AND gate; (b) DL OR gate; (c) DTL NAND gate. An example of a DTL gate is shown in Figure 10.2(c) (note the similarity between this circuit and hat in Figure 8.7), in which the DL circuit is the AND gate of Figure 10.2(a). Therefore, given that a ommon-emitter BJT is inherently an inverter (because when the base voltage grows, the collector voltge decreases), a NAND results from this association (AND + inverter). This can also be understood y simply observing the voltage on node x; when it is high, the BJT is turned ON, so y = V CEsat (~0.2 V) esults, while a low voltage on x turns the transistor OFF, raising the voltage of y towards V CC. ELD0001 Prof. Renan Sebem Aula 3 4 / 18

5 Famílias Lógicas Logic Families and I/Os Exemplo - TTL ND circuit constructed with TTL logic. ELD0001 Prof. Renan Sebem Aula 3 5 / 18

6 Lógica TTL Versões TTL: 74: Standard TTL; 74S: Schottky TTL; 74AS: Advanced Schottky TTL; 74LS: Low-power Schottky TTL; 74ALS: Advanced low-power Schottky TTL; 74F: Fast TTL. ELD0001 Prof. Renan Sebem Aula 3 6 / 18

A comparison between the TTL versions is presented in Figure 10.5. Note, for example, the different current capacities, speeds, and power consumptions.

7 A comparison between the TTL versions is presented in Figure Note, for example, the different current capacities, speeds, and power consumptions. For example, the last TTL version (F) has the lowest delay-power product among the fast versions. Other parameters from this table will be examined below. Lógica TTL Principais parâmetros das tecnologias TTL FIGURE Main parameters of TTL technologies used in the 74/54 series of digital ICs. ELD0001 Prof. Renan Sebem Aula 3 7 / 18

8 Lógica TTL Fan-in e Fan-out Fan-in é o número de entradas de uma porta lógica; Fan-out é o número máximo de conexões na saída de uma porta lógica. ELD0001 Prof. Renan Sebem Aula 3 8 / 18

9 Lógica TTL Limites de tensão e margem de ruído - TTL Emitter-Coupled Logic 225 itter-coupled Logic 225 E (a) Supply and minimum/maximum signal voltages for the TTL family; (b) Corresponding noise ins (a) Supply and minimum/maximum signal voltages for the TTL family; (b) Corresponding noise e meaning of the parameters above was seen in Section 1.8 and is repeated below. Veaning IL : Maximum of the parameters input voltage above guaranteed was seen to in be Section interpreted 1.8 and as is '0'. repeated below. ELD0001 Prof. Renan Sebem Aula 3 9 / 18

10 CMOS Principais vantagens da lógica CMOS em relação à TTL: Menor consumo de energia; Operação em frequências maiores. ELD0001 Prof. Renan Sebem Aula 3 10 / 18

11 CMOS Sub-famílias HC e HCT CMOS HC foi criada depois que a TTL; CMOS HC é incompatível com a TTL; CMOS HCT é compatível com TTL; CMOS HC e TTL podem ser utilizadas conjuntas desde que haja uma interface entre as portas lógicas. ELD0001 Prof. Renan Sebem Aula 3 11 / 18

12 HC and HCT CMOS Families CMOS We describe next two 5 V CMOS families, called HC and HCT, both employed in the 74/54-series of Exemplo digital ICs. - CMOS FIGURE CMOS gates: (a) Inverter; (b) 3-input NAND/AND; (c) 3-input NOR/OR. ELD0001 Prof. Renan Sebem Aula 3 12 / 18

13 CMOS 228 CHAPTER 10 Logic Families and I/Os Principais parâmetros das tecnologias CMOS HC e HCT FIGURE Main parameters of the HC and HCT CMOS families employed in the 74/54-series of digital ICs. The HC family is the CMOS counterpart of the TTL family. Like TTL, its nominal supply voltage is 5 V (though it can operate anywhere in the 2 V 6 V range). However, not all of its input voltages are compatible with TTL, so HC and TTL gates cannot be mixed directly. To cope with this limitation, a TTL- ELD0001 Prof. Renan Sebem Aula 3 13 / 18

14 S gate (or several CMOS gates), A would operate with very small currents, so V CMOS OL and V OH would most 0.1 V far from the rail voltages, yielding higher noise margins..6.6 Low-Voltage CMOS Limites de tensão e margem de ruído - CMOS mentioned above, modern designs employ almost exclusively low-voltage CMOS circuits. Even ugh.6 their Low-Voltage general architecture CMOS is still that seen in Chapters 4, 9, and again in this chapter, the supvoltage was above, reduced modern from designs 5 V to 3.3 employ V, then almost to 2.5 V, exclusively 1.8 V, and 1.5 low-voltage V. Recently, CMOS it was further circuits. reduced Even entioned h their general architecture is still that seen in Chapters 4, 9, and again in this chapter, the supoltage was reduced from 5 V to 3.3 V, then to 2.5 V, 1.8 V, and 1.5 V. Recently, it was further reduced URE (a) Voltage ranges for the HC CMOS family; (b) Corresponding noise margins. E (a) Voltage ranges for the HC CMOS family; (b) Corresponding noise margins. ELD0001 Prof. Renan Sebem Aula 3 14 / 18

15 CMOS Exemplo - CMOS dinâmica 10.8 Dynamic MOS Architectures FIGURE (a) Dynamic NAND and NOR gates; (b) Dynamic footed NAND and NOR ELD0001 Prof. Renan Sebem Aula 3 15 / 18

16 Bibliografia [1] Volnei A. Pedroni. Eletrônica digital moderna e VHDL: Princípios digitais, Eletrônica Digital, Projeto Digital, Microeletrônica e VHDL. Elsevier, ELD0001 Prof. Renan Sebem Aula 3 16 / 18

17 Aula 3 - Famílias lógicas Prof. Renan Sebem Disciplina de Eletrônica Digital Graduação em Engenharia Elétrica Universidade do Estado de Santa Catarina Joinville-SC Brasil 1 de março de 2016 Obrigado. ELD0001 Prof. Renan Sebem Aula 3 17 / 18

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