Disciplina de. Organização de Computadores Digitais

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1 USP - ICMC - SSC SSC Sist. Informação - 2o. Semestre 2014 Disciplina de Prof. Fernando Santos Osório fosorio [at] { icmc. usp. br, gmail. com } Página Pessoal: Lab. de Robótica Móvel 1 Out Material on-line: Wiki ICMC: Aula 10s

2 Apresentação da Aula Conteúdos Abordados: Microprocessadores RISC 1. Microprocessador RISC: MIPS e ARM 2. Arquitetura da Processador MIPS 3. Programação do Processador MIPS 4. Simulação do Processador MIPS 2 Out. 2014

3 Microprocessador RISC Comerciais Microprocessador Comerciais: Famosos MIPS e ARM => Origem MIPS: John L. Hennessy at Stanford University 1981: Microprocessor without Interlocked Pipeline Stages is a RISC processor developed by MIPS Technologies (formerly MIPS Computer Systems, Inc.). The early MIPS architectures were 32-bit, with 64-bit versions added later. Multiple revisions of the MIPS instruction set exist, including MIPS I, MIPS II, MIPS III, MIPS IV, MIPS V, MIPS32, and MIPS64. The current revisions are MIPS32 (for 32- bit) and MIPS64 (for 64-bit) ARM: Inspired by white papers on the Berkeley RISC proj. / Acorn Computers 3 Out /1990: Advanced RISC machines (ARM) spins out of Acorn & Apple Computers collaboration efforts with a charter to create new microprocessor standard. VLSI Technology becomes an ARM investor and the first Licensee of ARM processor IP.

4 Microprocessador RISC Arquitetura RISC Processadores Comerciais: MIPS 4 Out

5 Microprocessador RISC Arquitetura RISC Processadores Comerciais: ARM Advanced RISC Machines ARM Core Diagram 5 Agosto 2008

6 Microprocessador RISC Comerciais MIPS & ARM: Características - RISC Architetures - Bancos de Registradores - Instruções de tamanho fixo e regulares - Pipeline de instrução otimizado - Baixo Custo - Baixo Consumo - Alto desempenho 6 Out. 2014

7 Microprocessador RISC Comerciais Microprocessador Comerciais: Famosos MIPS e ARM => Produtos MIPS: Processors R2000, R3000, R4000, R6000, R8000,... MIPS32, MIPS64 Sony PS2, PS Portable, Qualcomm, Atheros, Broadcom, SGI Onyx ARM: 7 Out. 2014

8 Microprocessador RISC Comerciais Microprocessador Comerciais: Famosos MIPS e ARM => Produtos MIPS: Processors R2000, R3000, R4000, R6000, R8000,... MIPS32, MIPS64 Sony PS2, PS Portable, Qualcomm, Atheros, Broadcom, SGI Onyx ARM: 8 Out * ARM: Ver slides complementares

9 Microprocessador RISC: MIPS SIMULADOR do MIPS: SPIM Windows Linux GUI Line Cmd Refs.: Livro: Organização e Projeto de Computadores David A. Patterson & John L. Hennessy [Apêndice B] 9 Out Web site: James Larus

10 Microprocessador RISC: MIPS MIPS Registradores 10 Out. 2014

11 Microprocessador RISC: MIPS MIPS Instruções 11 Out * MIPS Instruction Set Ver Referências Complementares

12 Microprocessador RISC: MIPS MIPS Instruções CPU & FPU 12 Out. 2014

13 Microprocessador RISC: MIPS MIPS System Calls 13 Out. 2014

14 Microprocessador RISC: MIPS MIPS Instruções li = Load Immediate la = Load Address syscall = System Call (Software Interrupt Call) b = Unconditional Branch bgtz = Branch Greater than Zero bltz = Branch Less than Zero bgez = Branch Greater Equal Zero blez = Branch Less than Equal Zero +Infos: > Help do SPIM > Apendice Livro Hennessy (By Larus) 14 Out. 2014

15 Microprocessador RISC: MIPS MIPS Instruções # helloworld.s # # Print out "Hello World" # Copyright (c) 2013, James R. Larus. li = Load Immediate la = Load Address lw = Load Word (32 bits) syscall = System Call (Software Interrupt Call) msg:.data.asciiz "Hello World".text.globl main main: li $v0, 4 # syscall 4 (print_str) la $a0, msg # argument: string syscall # print the string 15 Out END: li $v0, 10 # exits program syscall

16 Microprocessador MIPS REFERÊNCIAS COMPLEMENTARES: MIPS & SPIM MIPS PROCESSOR SIMULADOR SPIM DOCUMENTAÇÃO: (Apêndice Livro Hennessy) 16 Out CODE Examples: (ver em: Information for the MIPS Simulator SPIM )

17 INFORMAÇÕES SOBRE A DISCIPLINA USP - Universidade de São Paulo - São Carlos, SP ICMC - Instituto de Ciências Matemáticas e de Computação SSC - Departamento de Sistemas de Computação Prof. Fernando Santos OSÓRIO Web institucional: Página pessoal: fosorio [at] icmc. usp. br ou fosorio [at] gmail. com Disciplina de / BSI Web disciplina: Wiki ICMC - > Programa, Material de Aulas, Critérios de Avaliação, > Lista de Exercícios, Trabalhos Práticos, Datas das Provas 17 Out. 2014

18 ARM PROCESSOR Slides Complementares ARM Agosto 2008

19 version Architecture Revisions ARM PROCESSOR ARMv7 ARM1156T2F-S ARM1136JF-S ARMv6 ARM102xE XScale TM ARM1176JZF-S ARM1026EJ-S ARMv5 ARM7TDMI-S StrongARM ARM9x6E ARM92xT ARM926EJ-S SC200 V4 SC100 ARM720T time XScale is a trademark of Intel Corporation 19

20 Data Sizes and Instruction Sets ARM PROCESSOR The ARM is a 32-bit architecture. When used in relation to the ARM: Byte means 8 bits Halfword means 16 bits (two bytes) Word means 32 bits (four bytes) Most ARM s implement two instruction sets 32-bit ARM Instruction Set 16-bit Thumb Instruction Set Jazelle cores can also execute Java bytecode 20

21 Processor Modes ARM PROCESSOR The ARM has seven basic operating modes: User : unprivileged mode under which most tasks run FIQ : entered when a high priority (fast) interrupt is raised IRQ : entered when a low priority (normal) interrupt is raised Supervisor : entered on reset and when a Software Interrupt instruction is executed Abort : used to handle memory access violations Undef : used to handle undefined instructions System : privileged mode using the same registers as user mode 21

22 The ARM Register Set ARM PROCESSOR Current Visible Registers IRQ FIQ SVC Undef Abort User Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) User FIQ IRQ SVC Undef Abort r8 r8 r9 r9 r10 r10 r11 r11 r12 r12 r13 (sp) r14 (lr) r13 (sp) r14 (lr) Banked out Registers r13 (sp) r13 (sp) r13 (sp) r13 (sp) r14 (lr) r14 (lr) r14 (lr) r14 (lr) cpsr spsr spsr spsr spsr spsr spsr 22

23 Program Status Registers ARM PROCESSOR N Z C V Q J U n d e f i n e d I F T mode f s x c Condition code flags N = Negative result from ALU Z = Zero result from ALU C = ALU operation Carried out V = ALU operation overflowed Sticky Overflow flag - Q flag Architecture 5TE/J only Indicates if saturation has occurred J bit Architecture 5TEJ only J = 1: Processor in Jazelle state Interrupt Disable bits. I = 1: Disables the IRQ. F = 1: Disables the FIQ. T Bit Architecture xt only T = 0: Processor in ARM state T = 1: Processor in Thumb state Mode bits Specify the processor mode 23

24 Program Counter (r15) ARM PROCESSOR When the processor is executing in ARM state: All instructions are 32 bits wide All instructions must be word aligned Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as instruction cannot be halfword or byte aligned) When the processor is executing in Thumb state: All instructions are 16 bits wide All instructions must be halfword aligned Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as instruction cannot be byte aligned) When the processor is executing in Jazelle state: All instructions are 8 bits wide Processor performs a word access to read 4 instructions at once 24

25 Conditional Execution and Flags ARM PROCESSOR ARM instructions can be made to execute conditionally by postfixing them with the appropriate condition code field. This improves code density and performance by reducing the number of forward branch instructions. CMP r3,#0 CMP r3,#0 BEQ skip ADDNE r0,r1,r2 ADD r0,r1,r2 skip By default, data processing instructions do not affect the condition code flags but the flags can be optionally set by using S. CMP does not need S. loop SUBS r1,r1,#1 decrement r1 and set flags BNE loop if Z flag clear then branch 25

26 Condition Codes ARM PROCESSOR The possible condition codes are listed below Note AL is the default and does not need to be specified Suffix EQ NE CS/HS CC/LO MI PL VS VC HI LS GE LT GT LE AL Description Equal Not equal Unsigned higher or same Unsigned lower Minus Positive or Zero Overflow No overflow Unsigned higher Unsigned lower or same Greater or equal Less than Greater than Less than or equal Always Flags tested Z=1 Z=0 C=1 C=0 N=1 N=0 V=1 V=0 C=1 & Z=0 C=0 or Z=1 N=V N!=V Z=0 & N=V Z=1 or N=!V 26

27 Conditional execution examples ARM PROCESSOR C source code ARM instructions if (r0 == 0) { r1 = r1 + 1; } else { r2 = r2 + 1; } unconditiona l CMP r0, #0 BNE else ADD r1, r1, #1 B end else ADD r2, r2, #1 end... 5 instructions 5 words 5 or 6 cycles conditional CMP r0, #0 ADDEQ r1, r1, #1 ADDNE r2, r2, # instructions 3 words 3 cycles 27

28 Data Processing Instructions ARM PROCESSOR Consist of : Arithmetic: ADD ADC SUB SBC RSB RSC Logical: AND ORR EOR BIC Comparisons: CMP CMN TST TEQ Data movement: MOV MVN These instructions only work on registers, NOT memory. Syntax: <Operation>{<cond>}{S} Rd, Rn, Operand2 Comparisons set flags only - they do not specify Rd Data movement does not specify Rn Second operand is sent to the ALU via barrel shifter. 28

29 Register Usage ARM PROCESSOR Arguments into function Result(s) from function otherwise corruptible (Additional parameters passed on stack) Register variables Must be preserved Register r0 r1 r2 r3 r4 r5 r6 r7 r8 r9/sb r10/sl r11 The compiler has a set of rules known as a Procedure Call Standard that determine how to pass parameters to a function (see AAPCS) CPSR flags may be corrupted by function call. Assembler code which links with compiled code must follow the AAPCS at external interfaces The AAPCS is part of the new ABI for the ARM Architecture - Stack base - Stack limit if software stack checking selected Scratch register (corruptible) Stack Pointer Link Register Program Counter r12 r13/sp r14/lr r15/pc - SP should always be 8-byte (2 word) aligned - R14 can be used as a temporary once value stacked 29

30 Pipeline changes for ARM9TDMI ARM PROCESSOR ARM7TDMI Instruction Fetch Thumb ARM decompress ARM decode Reg Select Reg Read Shift ALU Reg Write FETCH DECODE EXECUTE ARM9TDMI Instruction Fetch ARM or Thumb Inst Decode Reg Decode Reg Read Shift + ALU Memory Access Reg Write FETCH DECODE EXECUTE MEMORY WRITE 30

31 ARM10 vs. ARM11 Pipelines ARM PROCESSOR ARM10 Branch Prediction Instruction Fetch ARM or Thumb Instruction Decode Reg Read Shift + ALU Multiply Memory Access Multiply Add Reg Write FETCH ISSUE DECODE EXECUTE MEMORY WRITE ARM11 Shift ALU Saturate Fetch 1 Fetch 2 Decode Issue MAC 1 MAC 2 MAC 3 Write back Address Data Cache 1 Data Cache 2 31

32 ARM Referências: * Slides ARM - Material disponibilizado em: ARM Referências Complementares: * History * Company * Arquitetura Processador (Wikipedia) 32