MODELOS : LC3258WDA / LC4058FDA - SEMP /LE3264(A)W - STI

Transcrição

1 MSV()-09 MANUAL D SRVÇO LVSORS LD MODLOS : LWDA / L0FDA - SMP /L(A)W - S SPFAÇÕS e n s ã o d e r e d e : V ~ (0 H z) auto m á o n s u m o m é d i o L W D A ( has s i R V00) W L 0F D A ( has s i R V00) W L (A )W ( has s i A L00) W o n s u m o S t a n d b y ( o do s o s m o delo s ): < W P o t ê n c i a d e á u d i o L W D A / L (A )W W + W (R M S) / L 0F D A W + 0 W (R M S) / R e s o l u ç a o L W D A / L (A )W x L 0F D A x 00 o n t r a s t e L (A )W (es tático ) x L W D A (es tático ) x L 0F D A (es tático ) x o hm o hm r i l h o L (A )W cd/m ² L W D A cd/m ² L 0F D A cd/m ² e m p o d e R e s p o s t a... L (A )W , m s L W D A , m s L 0F D A ,0 m s P e s o L (A )W , Kg L W D A , Kg L 0F D A , Kg D i m e n s õ e s ( L x A x P ) ---- L (A )W co m pedes tal (s em pedes tal) x90x (X9X) L W D A co m pedes tal (s em pedes tal) x0x (9XX) L 0F D A co m pedes tal (s em pedes tal) xx0 (9XX) o n t r o l e R e m o t o M o delo s L / M o delo s L (A )W o n d i ç õ e s d e f u n c i o n a m e n t o em peratura: 0 ~ Um idade: 0 ~ 0% s em co ndens ação. S i n t o n i z a d o r A n a l ó g i c o m pedância de entrada de antena: o hm -tipo des balanceada para VH F /UH F / A O N :. Sis tem a de s into nia f.s. (F requency s ynthetizer)-p LL Sis tem a de telev is ão : P adrão M - linhas anais de recepção : F aixa - anais a O F F A R -, M H z a, M H z-vh F a A O -, M H z a, M H z F aixa - anais a LL O F F A R -, M H z a, M H z-vh F a A O -, M H z a, M H z F aixa -anais M M a O F F A R -, M H z a 0, M H z-uh F a A O -, M H z a, M H z F reqüências interm ediárias : P o rtado ra de v ídeo , M H z P o rtado ra de s o m , M H z/,m H z P o rtado ra de cro m a , M H z F reqüências s ubpo rtado ras de cro m a: ,m H z (P A L M ),0 M H z ----(P A L N ),9 M H z ----(N S ) S i n t o n i z a d o r D i g i t a l m pedância de entrada de antena: o hm -tipo des balanceada para UH F. F reqüência de entrada: ~ H z M o do O F D M : K o ns telação : Q P SK, D Q P SK, Q A M, Q A M axa interna do có digo : /, /, /, /, / nterv alo de guarda: /, /, /, / Sens ibilidade: d K, Q A M, /, / a) canal analó gico adjacente: N m ax -d / N + -d m áxim o b) canal digital adjacente: N - m ax -d / N +-9d m áxim o c) análo ga do co -canal: m áxim o do d D ígito de canais : d m áxim o SMP OSHA

2 NDÍ specificações : capa Índice : nformações / nstruções de ajuste : squema létrico da Placa Principal L(A)W : squema létrico da Placa Demoduladora L(A)W : squema létrico da Placa Principal L/0 : squema elétrico da Placa Sensor/LD : squema elétrico da Placa Fonte L(A)W : squema elétrico da Placa Fonte L : squema elétrico da Placa Fonte L0 : Localização omponentes P Principal L/0 : Localização omponentes P Principal L(A)W : SMP OSHA

3 NFORMAÇÕS / NSRUÇÕS D AJUSS VRFAÇÃO DA VRSÃO DO SOFWAR. No Menu onfiguração, selecionar "nformação do sistema". DSLOQUO DO APARLHO. aso o cliente esquecer o código de bloqueio de canais, das entradas/classificação indicativa, entre com o código 0; ; ; para desbloquear e entre com nova senha. A senha inicial de fábrica é ; ; ;. NRAR NO MODO SRVÇO. Pressione a tecla MNU, selecione ontraste e pressione a sequencia "9; ; ; " Menu do modo serviço. - Hotkey On / Off Mostra o modo fábrica indicando a versão do Software, piscando na tela. - urning Mode On / Off omuta as telas R, G,, White, lack. Para sair, pressione a tecla Menu do aparelho. - AD Sem função - White alance > Ajuste da escala de cinza das entradas, omponente, AV, HDM, P, é ajustado somente no modo HDM. - Reset Shop > Dá o reset em todos os ajustes e deixa no modo loja. - reset All > Dá o reset geral, inclusive nos canais sintonizados, ao ligar, entra na tela de instalação. - Power mode Last Sta/Standby Muda o modo do estado de retorno de energia, último modo ou standby - US lone opia dados de uma V para outro através do US. opia os ajustes do usuário, lista de canais, dados do PROM, clona a V. 9- Other Mostra a tela de informação do sistema em detalhes. O D ajusta o painel de acordo com o modelo. NRAR NO MODO HOL. Selecionar contraste no MNU imagem. HAGM NFORMAÇÕS ÚS MODO D SRVÇO MODO HOL PRÉ-AJUSS Sem entrar no ajuste do contraste, pressionar a sequencia "9; ; ; ". Hotel mode On/Off Habilita e desabilita o modo Hotel. Display message On/Off Habilita ou desabilita mensagem. mensagem Habilitar com Display message On e digitar com as teclas numéricas, total de 9 caracteres por linha. MODO HOL PRÉ-AJUSS (cont.) eclas x caracteres: - a; b; c; A; ; ; - d; e; f; D; ; F; - g; h; i; G; H; ; - j; k; l; J; K; L; - m; n; o; M; N; O; - p; q; r; P; Q; R; - s; t; u; S; ; U; - v; w; x; V; W; X; 9 - y; z; Y; Z; ; -;.; 0 h lock Ativ/nat loqueia a função sintonia de canais. MAX VOL 0 Faz o pré-ajuste do volume máximo. Auto set Ativ/nat Ativa os pré-ajuste do som e imagem Pic preset Filme Seleciona a preferencia de imagem que a V vai ligar. Filme; Padrão; Usuário; Dinâmico Sound preset Desl Seleciona a preferencia de som que a V vai ligar. Desl.;Rok; Pop; Ao Vivo; Dança; echno; lássica; Suave Pré-ajustes Vol. 0 Pré- ajuste do volume que vai ligar. Pré-ajustes ntr. V Pré-determina a entrada em que irá ligar. V, AV, AV, omponent, P, HDM, HDM, HDM. Pré-ajustes an. Pré-determina o canal em que irá ligar. Key-lock Ativ/nat Desabilita as teclas do V. Modo Ligar Arranque Determina o modo de retorno da V ao ligar na tomada. Arranque ou m espera. US lone Mode All Faz clone de: All; hannel, User Setting, PROM. V to US Do Faz clone dos ajustes do V para Pen Drive. US to V Do lona os ajustes contidos no Pen Drive para o V. NFORMAÇÃO/GRAVAÇÃO D SOFWAR GRAVAÇÃO D PROGRAMAS (SOFWAR). SARUP Gravado com GANG WRR no - U0 Flash NQ. Versão V-OM00-LFV0.bin DD Gravado no U0 M0 com LAP OP e jiga específico. Versão V-OM00-LDV00 NVM Gravado no U0 M com LAP OP e jiga específico. Versão NVM Data.bin e Key_code.bin (HDP) AUALZAÇÃO D SOFWAR AUALZAÇÃO DO SOFWAR. A atualização do software é feito via entrada US, com software copiado no pen Drive no formato abaixo. O software é comum para os modelos L e L0 specífico para o modelo L. AUALZAÇÃO D SOFWAR (cont.) Atualização: Desconectar o cabo de força da tomada A, inserir o Pen drive com o software na entrada US e com a tecla POWR do aparelho pressionado, conectar o cabo de força na tomada A. onfirmar o acendimento alternado do LD vermelho e verde e soltar a tecla. Aguardar o LD parar de piscar, desconectar o cabo de força e retirar o Pen drive. om o MNU, reiniciar a V para colocar em funcionamento normal. DNFAÇÃO DO PANL/MODLO DNFAÇÃO DO PANL/MODLO. Ao trocar a placa/memória por uma placa de um outro modelo, há a necessidade de informar ao software em qual painel/modelo será utilizado. Após a troca da placa/memórias, o sistema não reconhece automaticamente o painel que será utilizado e a tela poderá ficar totalmente escura, onde nem o MNU aparece. om o LD aceso, pressionar a sequencia abaixo para reconhecimento do painel/modelo, mesmo com a tela totalmente escura. L MNU + 0 L MNU + 0 L MNU

4 SQUMAS LÉROS Placa Principal L(A)W ack Light circuit +V VS +V MAN_POWR _P MAN_POWR H = > POWR_OFF LO = > POWR_ON ADN_SRV R0 K R 0K R 0K Q0 90 R K L 0 PAN_ON/OFF ON/OFF_PWR PAN_ON/OFF ON/OFF_PWR PAN_ON/OFF 0 _P P00 9 PANL_DM S PANL_DM S_POWR R N/0K DMMNG DVDDV R K +V R N/K D0 N/LL L_DMMNG R R K N/ Q0 90 R0 VR_X 0 N/U L 0 PANL_DM POWR 0

5 0 SQUMAS LÉROS Placa Principal L(A)W N OU S N SW OMP F SS N close to P00 0P L0 U0 MP N/K R Q0 N/90 Q0 90 R K R 0 VS VK U 0 N/00U V 0 0U V N/0K R U N/ U0 N/R9- N/00U V V R 0K R 0K S_POWR VK R K VS R0 0K R9 K R 00K R S_POWR 0 9 VS L00 UH S_POWR 00P 0.0U 00U V 0P ON/OFF_PWR ON/OFF_PWR S_POWR MAN_POWR PAN_ON/OFF PANL_DM OPWRS ON/OFF_PWR POWR

6 0 SQUMAS LÉROS Placa Principal L(A)W D DA G G S D DA S /ADJ OU VN VOU VN ADJ/ VOU VN ADJ/ /ADJ OU VN /ADJ OU VN S N SW OMP F SS N V LGA PHAS OO F UGA VN Vout=0.*(0+00)/0=.0 Max.A mo L0 0UH RS_V V R R R R 00P N/U V 0 N/0U 0 0U U 0 N/ 0.0U N/0U V V 0U 9 V 0U 99 L 0 AVDDV AVDDV DVDDV V +V U0 R0 0.0U U00 MP9DN 9 AVDDV L0 0 L 0 0 L 0 L L0 0 R0 R00 N/00U V L 0 0 L 0 L0 N/0U V N/0 L00 N/0 L09 V 0U V 00 0U V LDS U0 N/00P U0 N/LDS U0 N/AZ0 U09 AZ0 U0 ASAD 09 U L 0 DVDDV +V +V R K R +/-% 00U V U R K % R 0K % L0 UH SR D00 K R 00P R R0 R0 R +V MAN_POWR AVDDV AVDDV 00U V 00U V 0 9 Z0 Q00 DN0L D0 LL 0 U MAN_POWR V POWR

7 0 SQUMAS LÉROS Placa Principal L(A)W /ADJ OU VN VOU VN ADJ/ VOU VN ADJ/ protection circuit U=-AZ0-AD 0 U V R /% R9 K R K R K 00U V 0 N/00U V R0 R R9 R R R UNR_V DDRV +V L0 0 R R U N/AZ0 U AZ R N/R V 0U R R 9 N/00U V D0 LL D0 LL D0 LL D0 LL R K R K R0 K R K V VS Q0 90 LL D0 UNR_V U0 LDS0/V Z0 V DDRV AVDDV DVDDV UNR_V ADN_SRV 0V +V DDRV POWR

8 0 SQUMAS LÉROS Placa Principal L(A)W SDA DF+ + AF RF-AG N N AS SL F_AG DF- + N SDA SL N N RF-AG N DF+ DF- N 0 9 U U0 F+ F- FA- R UNR_FA+ R _V AS FA+ UNR_LOK R0 0 _SDA _SL R_AG UNR_V_ UNR_V_ L09 L0 UNR_RF_AG UNR_RF_AG _SDA _SDA _SL UNR_F_AG R0 0K AS R0 0 L0 L0 0 0P R09 /N N/ UNR_V L U V P 0 0.0U 0 0.0U UNR_DAA RF_AG UNR_FA- UNR_FA+ _SL UNR_FA- _V UNR/DMOD D

9 09 SQUMAS LÉROS Placa Principal L(A)W band filter struction follow M0 DMOD_FA+ L 0.UH L 0.UH R9 R99 N/0.0U 0 N/0.0U R0 N/ R N/ R9 N/R R N/9R9 R N/9R9 R R 0.0U 0.0U R N/9R9 P 09 P 0.0U R0 N/ 9 0.0U R0 N/ R K R K FA_N- R R L N/0.UH L 0.UH L99 N/0.UH 9 N/0P P P UNR_LOK UNR_DAA FA+_D FA+_D FA-_D FA-_D F_AG R0 0 DMOD_FA- UNR_FA- UNR_FA+ N/0 R00 R0 N/0 _FA+ 0 0P 0P 0P R0 0 0K R 0.0U 0 0P 9 0P UNR_V F_AG UNR_SL UNR_SDA OSL0 OSDA0 UNR_F_AG FA N- FA N+ _FA- UNR_FA- UNR_FA+ 0 N/P 0 N/P 0 N/P L00 N/0.UH N/P 0 N/P FA_N+ UNR/DMOD D

10 0 SQUMAS LÉROS Placa Principal L(A)W DMOD D ONNOR for AS R 0 9 P0 0 9 P00 UNR_SDA UNR_SL D_FA+ D_FA- D_POWR Z OSDA0 OSL0 D_RS GPO_ DMOD_FA+ DMOD_FA- Z Z 0P 0P 0P R0 K 0P Z09 DMO_SYN UNR_SL DMO_DAA0 DMO_POWRDOWN D_F_AG DMOD_RS DMOD_RS DMO_DAA OSDA0 OSL0 DMOD_RS DMO_DAA DMO_DAA DMO_DAA DMO_DAA DMO_LK OSDA0 DMO_DAA DMO_DAA DMO_VALD OSL0 UNR_SDA N AVDDV DMO_POWRDOWN UNR/DMOD D

11 SQUMAS LÉROS Placa Principal L(A)W V S A Y V Z lose to tunter LOS O M R 0K U00 LVGGV R N/ D_F_AG_ D_F_AG D_F_AG_ +V +V R 00 N/0U N/ U0 N/LVG R A_RF_AG AOSDAA AOSDAA F_AG A_F_AG RF_AG R N/ R R R0 R R R R9 R S_SYN_N D_VALD D_SYN D_LK D_DA0 S_LK_N DMO_LK S_VALD_N S_D0_N DMO_VALD DMO_SYN DMO_DAA0 UNR/DMOD D

12 SQUMAS LÉROS Placa Principal L(A)W RX+ RX- RX+ RX- RX0+ RX0- RX+ RX- N N DDLK DDDA V HPD RX+ RX- RX+ RX- RX0+ RX0- RX+ RX- N N DDLK DDDA V HPD SDA SL WP V A A A0 SDA SL WP V A A A0 H:WP,L:WR HDM HDM H:WP,L:WR HDM_DD HDM_DD U0 A0 U0 A0 HDM_AR R N/K R0 N/K 90 Q0 R9 K R 00K 90 Q0 R K R K R 00K R K K R0 HDM_V K R0 R K K R0 HDM_V HDM RXLKN RXLKP RX0N RX0P RXN RXP RXN RXP R0 K HDM RXLKN RX0N RXLKP RX0P RXN RXP RXN RXP H_ SDA_ SL_ H_ SDA_ SL_ P P0 0K R09 R0 0K WP_ WP_ R0 K DDSL DDSDA R 0 0 R R0 0 0 R9 DDSDA DDSL R 0K 0 DDSL DDSDA HDM_V R 0K DDSL DDSDA HDM_V HOPLUG HOPLUG HDM

13 SQUMAS LÉROS Placa Principal L(A)W RX+ RX- RX+ RX- RX0+ RX0- RX+ RX- N N DDLK DDDA V HPD SDA SL WP V A A A0 H:WP,L:WR HDM HDM_DD U0 A0 R N/K R9 K 90 Q0 R K R 00K 0K R0 HDM_V R00 K HDM RXLKN RXLKP RX0N RX0P RXN RXP RXN RXP H_ SDA_ SL_ P00 WP_ R0 K K R0 0 R R 0 DDSDA DDSL R 0K DDSL DDSDA HDM_V HOPLUG V A O Y HDM_AR R R R N/K R N/0K R R0 0K R R K U0 LVGGW U R R AVDDV +V HDM_AR M0L_SPDF GPO_0 HDM

14 SQUMAS LÉROS Placa Principal L(A)W V- DNG- DPOS- - MN-HOL MN-HOL Y/AV P/R PR/L US POR AV N(side) P0 VSP VS_ AVL_N AV_L_N VS_ AVR_N AVR_N AV_R AV_L AV_ VS_ U+ U- U_POW P0 F0 F0 F0 F0 F00 L0 L0 L0 0P 0P U U P 0 0.0U 9 00U V N/0U N/0P N/0P R K R K R 0K R0 0K R9 R R 0 R R R R AVL_N Z00 +V US_DM US_DP AV_R_N HDM

15 SQUMAS LÉROS Placa Principal L(A)W SL_SNK SDA_SNK POW_SNK HPD SDA SL Z V X Y Z Z HPD_SNK Y Z _RS A POW A A HPD POW A POW V A A SL RX POWDN SDA_L SL_L _ADDR Y Y SL SDA A A V A V HPD N A SDA A A (9) N/K R N/K R R N/K N/90 Q00 RXP RXN R 0 N/ R N/.K R R R0 R9 M_RX_ M_RX_ M_RX_ M_RX_ M_RX_0 M_RX_ U00 PS HDM_ R 0 HDM V_HDM R K K R D00 LL VS R K R K 0 L00 HDM_V HDM_V R K V_HDM R K V_HDM V_HDM U 0 AVDDV 0 0U R 0 OSDA0 OSL0 P 0 0 P M_RX_ M_RX_ V_HDM V_HDM HDM_SL HDM_SDA K R HDM_HPD V_HDM V_HDM HDM_V RXN RXP DDSDA DDSL HOPLUG RX0P RX0N HOPLUG DDSDA DDSL RXLKN RXLKP HOPLUG DDSDA DDSL RXLKN RXLKP RX0N RX0P RXN RXP RXN RXP RXLKN RXLKP RX0N RX0P RXN RXP RXN RXP HDM

16 SQUMAS LÉROS Placa Principal L(A)W close to YPbPr connector close to M0 YPPR N R 0 00P SOY P P0 GRN LU RD P0 WH RD Y Y_N_ P_N_ PR_N_ YRL_N YRR_N Z9 YUV_L YUV_R L P L PR L F YRL_N YRR_N F9 L0 L0 F F F R9 R R R R R 0P R R R R R R PR_N 0 0P Y_N P_N R 0K R 0K R0 K P R P P R K Y_N P_N PR_N OMX 0 U R 0 R N/0 R 0 R 0 R9 N/0 R90 N/0 0 U R U 0.0U 0.0U 0.0U YPPR_L_N YPPR_R_N OM PRP YP PP P Y/AV PR/L P/R SAR N R L PR_N_ P_N_ Y_N_ YRR_N YRL_N ONLY FOR M MARK S_AUR_OU S_AUL_OU S_AUR_N S_AUL_N S N S_G_N S_R_N S_AV_N S_F_N S_AV_OU S_FS_N _YP _YPA SR_OU SL_OU SR_N SL_N S_ S_G S_R S_AV_N F S_AV_OU FS P0 MN SAR 00//0 YPPR/US/SAR/SPDF

17 SQUMAS LÉROS Placa Principal L(A)W +V SPDF OU(OPAL) M0L_SPDF Near onnector R0 R 0 N/0.0U R N/0 SPDF SPDF_ 0 R9 S_+V VN V P0 DRV X LD P0 LAK R0 0 VGA_XD VS VGA_RXD R 0 R N/0 R N/0K R N/0 U0X GPO_ R99 N/K Q0 N/Z R N/ R N/0K Q0 N/Z R N/ Q0 N/Z UX Function Select Function Select S_FS_N F R N/VA R 0K SAR_FS0 R0 K FAS LANKNG S_F_N R F0 N/VA R K R R SOY0 close to VGA connector YPPR/US/SAR/SPDF

18 SQUMAS LÉROS Placa Principal L(A)W VGA ONNOR close to VGA connector close to M0 00P R 0 VGA_XD R Z0 G HSYN VSYN VSYN_N VGA_RXD VGA_SL VGASL_N L L L R0 N/VA N/VA R00 R0 N/VA D00 AV0 R0 N/VA R0 N/VA 0 9 P0 R 0.0U R R R R 0 0P 9 0.0U R R 0P R R0 0P 0.0U 0 R9 R R 0.0U R R 0P 0P VGA_PLUGPWR VGA_PLUGPWR R 0K R0 0K F0 F0 F0 F0 F00 R 0 Z Z VGASL VGASDA_N HSYN_N GRN RD VGA_PLUGPWR +V VGASDA VGASDA_N VGASL_N RP SOG GP P RD LU GRN VGAOM LU VGA_XD YPPR/US/SAR/SPDF

19 9 SQUMAS LÉROS Placa Principal L(A)W R L VGA AUDO NPU VGA_R VGA_L L00 L R R9 N/K R N/K N/VA R0 R0 N/VA R 0K R 0K R K R K Z0 R P00 0 U 0 U F0 F0 0P 0 0P F0 0P 0P F VGA_L_N VGA_R_N HSYN VSYN HSYN_N VSYN_N VGA_AUDO_R_N VGA_AUDO_L_N YPPR/US/SAR/SPDF V- DNG- DPOS- - MN-HOL MN-HOL NAR M0 UAR OU US POR 0 L09 L0 R VA R VA _UA P0 R R D+ D- US_V UXD U0XD R R 00 N/0U 9 N/0P 0 00U V N/0P L0 P0 Z0 VS R0 K R9 K F 0P +V 0P F F F0 U0XD UXD VS US_DM0 US_DP0 UX U0X

20 0 SQUMAS LÉROS Placa Principal L(A)W Y/AV P/R PR/L Y/AV P/R PR/L ONLY FOR M MARK NARLY ONNOR NARLY VS/RG N AUDO NPU VS OU NARLY ONNOR NARLY AUDO OU AV N AV OU P9 P99 _AVO _AV L0 R K R K R 0K R 0K S_AV_OU S_AUL_OU S_AUL_N S_AUR_N S_AV_N N/P R S_AV_N R 0 R 0 R 0 R9 0 R 0 N/VA R N/VA R R N/VA R0 N/VA R09 N/VA R0 N/VA R0 N/VA 0P 0P 0.0U L0 0 L0 0 R9 R R F F P L0.UH 0.0U 0P R R 0P R R 0.0U 0 0.0U R R 9 0P 0.0U R R R R 0P R 0 0 U 0 U 0P F F 0P F F F L0 F09 F0 SARL_PA S_AUR_OU S_AUL_OU VS_OU S_G_N Y0P S_AUL_N S_AUR_N SAR_R_N SAR_L_N P0P OM0 S_R_N VSP S N PR0P S_AV_OU SARR_PA 0.0U VS_OM S_AUR_OU YPPR/US/SAR/SPDF

21 SQUMAS LÉROS Placa Principal L(A)W M0 FSR_WR GPO VO_ AVDD_VPLL AP AN AP AN AP AN AKP AKN AP AN AP AN A0P A0N AVDD_LVDSA AVDD_LVDSA AOP AON AOP AON AOP AON AOKP AOKN AOP AON AOP AON AO0P AO0N VK VK VK AVDD_MMPLL AVSS_MMPLL ROD/RK RA/RA0 RA/RA RA/RA RA/RA RA/RA RA0/RA RA/RA RAS/RA RS_/RRAS_ RRAS_/RAS_ RA9/RW_ VO_ RA/RA0 RA/RA RA/RA9 N/RRS_ RA/RA RA/RA RA0/RA RA/RA RA0/RA RA/RA0 RW_/RS_ RK/ROD GPO GPO GPO GPO GPO GPO GPO GPO0 GPO GPO GPO0 VO_ VK PGO POW_ PAAL PAL PO_ PAR_ POO_ PO0_ PDD VO_ PDD PDD PDD PDD PDD PDD PDD0 _N SP_L SP_DAA SP_LK VK VO_ DMOD_SDAA0 DMOD_SSYN DMOD_SVAL DMOD_SLK OSDA OSL DMOD_RS RF_AG F_AG AOLRK AOSDAA0 AOMLK AOK AOSDAA ASPDF VK VK0 AR_ADA AR0_ADA AL_ADA AL0_ADA AVSS_DA AVDD_DA AVDD_AAD ANO_L_AAD VMD_AAD AN0_R_AAD LOUP VK RVRF RDQ/RDQ RDQ/RDQ JK JMS JD VO_ RDQ/RDQ RDQ/RDQ0 RDQ/RDQ RDQ9/RDQ9 VO_ RDQ/RDQ RDQ/RDQ RDQM/RDQM VK RDQS0/RDQS0 RDQSO_/RDQS0_ RDQM0/RDQM0 VO_ RDQS/RDQS RDQS_/RDQS_ RDQ/RDQ RDQ/RDQ VO_ RDQ0/RDQ0 RDQ/RDQ RDQ/RDQ RDQ0/RDQ VO_ RDQ/RDQ RDQ/RDQ VO_ RLK0/RLK0 RLK0_/RLK0_ VK JDO JRS_ OPWM0 ORS_ PWRV HDM_HPD HDM_SL HDM_SDA HDM_ AVDD_HDM RX_ RX_ RX_ RX_ RX_0 RX_0 RX_ RX_ AVDD_HDM US_P_VR AVDD_US_P US_P_DP0 US_P_DM0 US_P_DP US_P_DM VK VO_ AVDD_XAL_S XAL XALO AVDD_DMOD AVSS_DMOD AVSS_DMOD AVDD_FPGA ADNN_DMOD ADP_DMOD AVDD_DMOD AVDD_VS VS0P VS_OM VSP SY0 S0 SY S AVDD_PLL VK9 FS_VDA AVDD_VDA VDA_OU VDA_OU AVSS_RG AVDD_RG PR0P P0P OM0 Y0P SOY0 PRP PP OM YP SOY RP OM GP SOG P HSYN VSYN AVDD_VGA_S AVDD0_LDO ADN_SRV ADN_SRV ADN_SRV ADN_SRV ADN0_SRV VK VGA_SL VGA_SDA OPWRS OPRL OPRL0 OR U0X UX AVDD_PDM_S OPRL OPRL OPRL OPRL PAD_ FLASH AUDO LVDS OU _S N HDM* US* JAG VGA YPPR/DVD SAR/YPPR S_VS/AV SAR/AV Analog F N DDR R N/0K R N/0K R0 0K JDO JK JMS JD R K AVDD0_LDO 0 N/U V MU_RS M0L_RF_AG R R R0 0K 9 0.0U N/000P R N/00K AVDD_DA ADN_SRV M_RX_ R09 K M0L_F_AG R 00K U00 M0 R 0K R R 0 0.0U DDRV R0 % R0 K % R00 K % R0 K U 0P 0P AVDDV SDA0 OSDA0 A_RF_AG SL0 OSL0 A_F_AG OPRL OPRL OPRL OPRL VS UX U0X OPRL0 OPRL OPWRS VGASDA VGASL VK SAR_FS0 ADN_SRV KY VS_ VSYN HSYN P SOG GP VGAOM RP SOY YP OM PP PRP SOY0 Y0P OM0 P0P PR0P AVDDV_ UNR_YPASS_OU MONOR_OU AVDDV VK AVDDV VSP S0 SY0 S VS_OM VSP AVDDV_ AVDDV_ FA_N+ FA_N- AVDDV_ AVDDV_ OXALO OXAL VS DVDDV VK US_DM US_DP US_DM0 US_DP0 AVDDV AVDDV_ M_RX_ M_RX_0 M_RX_0 M_RX_ M_RX_ M_RX_ M_RX_ AVDDV_ HDM_ HDM_SDA HDM_SL HDM_HPD PWRV L_DMMNG JDO VK RLK0# RLK0 DDRV RDQ RDQ DDRV RDQ RDQ RDQ RDQ0 DDRV RDQ RDQ RDQS# RDQS DDRV RDQM0 RDQS0# RDQS0 VK RDQM RDQ RDQ DDRV RDQ9 RDQ RDQ0 RDQ DDRV JD JMS JK RDQ RDQ VK AN0_R_AAD AN0_L_AAD AVDDV_ AVDD_DA AL0O ALO AR0O ARO VK M0L_SPDF AOSDAA AOLK AOMLK AOSDAA0 AOLRK DMOD_RS SL0 SDA0 S_LK_N S_VALD_N S_SYN_N S_D0_N DVDDV VK SP_LK SP_DAA SP_L _N# PDD0 PDD PDD PDD PDD PDD PDD DVDDV PDD PO0# POO# PAR# PO# PAL PAAL POW# GPO_ VK DVDDV GPO_0 GPO_ GPO_ GPO_0 GPO_ GPO_ GPO_ GPO_ GPO_ GPO_ GPO OD _S# _A0 _A _A _A _A _A _RS# _A9 _A _A0 DDRV _W# _AS# _RAS# _A _A _A _A _A _A _A _A0 _K AVDDV VK X_AO0N X_AO0P X_AON X_AOP X_AON X_AOP X_AOKN X_AOKP X_AON X_AOP X_AON X_AOP X_AON X_AOP AVDDV X_A0N X_A0P X_AN X_AP X_AN X_AP X_AKN X_AKP X_AN X_AP X_AN X_AP X_AN X_AP DVDDV LVDS_PWR_N VMD_AAD RVRF JRS# US_VR ORS# VDA_FS ADN_SRV OR_OU AVDDV

22 SQUMAS LÉROS Placa Principal L(A)W DDRV DDR O POWR(close to chip) DDRV 09 0U V 0 U U DDR DVDDV.V O POWR(close to chip) VK core power(close to chip) DVDDV VK 0 U 0 0U V 0 U M0

23 SQUMAS LÉROS Placa Principal L(A)W M0 opctrl AOSDAA opctrl SRAPPNG strapping mode+m+serial boot ROM boot+m mode+m+serial boot ROM boot+m R K R R R R0 R9 R R R R VS R U OXALO R0 N/M R0 R0 N/ R N/K R N/K R N/K VS_ AVDDV R9 K R0 K R0 K AVDDV_ AVDDV_ AVDDV_ AVDDV_ AVDDV_ AVDDV_ P X00 M P DVDDV VS MONOR_OU VS_OU AVDD0_LDO OXAL OPRL OPRL AOSDAA UNR_YPASS_OU AVDDV AVDDV_ AVDDV_ VS

24 SQUMAS LÉROS Placa Principal L(A)W VS VS Standby power lose to pin of U VS_ 0 U AVDDV AVDDV AVDDV_ AVDDV_ AVDDV_ 00 U 0 lose to pin of U AVDDV AVDDV AVDDV_ AVDDV_ AVDDV_ AVDDV_ AVDDV_ 0 U 9 lose to pin of U M0

25 SQUMAS LÉROS Placa Principal L(A)W AVDDV _AV VK _DV0 L0 N/0 0 N/0U N/ N/ L00 N/0 N/U V 0 N/U 9 N/ 0 N/ N/ 0 N/ _DV _V _V _V R N/0K R N/0K R N/0K R N/0K R N/0K R N/0K R 0K _# _D# _D# _VS# _RQ# _OULK _WA# N/ N/ LOS O ONNOR S0 S S S NORMAL 0 X X X M NSYN N/0P N/0P M NVALD S0 S S S SP AS DVS AS 0 0 M

26 SQUMAS LÉROS Placa Principal L(A)W _DV R0 N/0K R0 N/0K R0 N/0K R0 N/0K HP_RL _OUDAA _OUDAA _OUDAA N/0K R0 N/0K R09 LOS O M0X _SP_LK _SP_DAA _SP_L N/0K R0 R N/ R N/ N/0K R N/ R0 SP_LK SP_DAA SP_L N/0P N/0P S_SYN_N N/R S_D0_N N/R S_VALD_N N/R N/0P S_LK_N N/R N/0P R R9 R R L0 N/ L0 N/ L0 N/ N/ L0 _S_SYNO _S_DAAO _S_VALDO _S_KO _N R N/ _N# R K M

27 SQUMAS LÉROS Placa Principal L(A)W M SP-L SP-DAA SP-LK PVR_S_DAA PVR_S_DAA0 PVR_S_SYN PVR_S_VAL PVR_S_LK _S_DAA0 _S_SYN _S_VAL _S_LK DVSS_ DVDD_ DMOD_S_SYN DMOD_S_VAL DMOD_S_LK DMOD_S_DAA0 AVSS_ P AVSS_ AVSS_ AVDD_ AVDD_ FPGA_NN AVDD_ DVSS_ UNR_DAA RF_AG S_S_SYN S_S_DAA0 DVDD_ M_RS_ DVDD0_ AVDD_ X_LKSL S_S_DAA S_S_DAA S_S_DAA D_ D D D D F_AG DVDD A0 O_ OWR_ A DVDD0_ A S_S_DAA A DVDD_ ADN0 N AVDD XAL XALO ORD_ AVSS FPGA_NP AVDD_ W_ A RADY D DVDD0_ UNR_LK S_S_LK S_S_VAL DVSS_ S_S_DAA S_S_DAA D S_S_DAA HP_RL D D D D DVSS DVSS_ VS_ A A9 A DVSS_ A A9 A0 A0 D D0 A A A A A A A VS_ A VD A MA_RS A WA_ A VD A DVDD_ DVSS_ A RG_ DVSS_ DVDD0_ D9 D D0 D D N DVSS_9 DVDD_ A down:signle end up:differential N/0K R0 0 N/P N/P 0 X00N/M R N/K R N/ U00 N/MA M NDAA0 SNDAA0 _DV SNDAA _D# _D M OUDAA R N/0K _GPO9 _GPO M NDAA _D _DV M NDAA _A _A M NLK _SP_DAA _SP_L _SP_LK R N/M _DV _DV0 _AV _AV _DV _DV _DV _AV _AV _AV _DV0 _DV0 _AV _AV _DV0 _S_DAAO _S_KO _S_VALDO _S_SYNO GPO_0 _A _N _D# _D M OUDAA _D M OUDAA _RG# _A _A M OUSYN _A _WA# _A _RS _A M OUVALD M NVALD M OULK _A M NDAA _A M NDAA M NDAA M NDAA _D0 M OUDAA0 _A0 _A9 _A _VS# _## M OUDAA M OUDAA M OUDAA HP_RL SNDAA SNDAA SVALD SLK UNR_SL _D _RQ# M NDAA _W## _FA+ _ORD## _A SNDAA M NSYN _OWR## _O## _A0 D_F_AG M OUDAA _D _D SNDAA SNDAA SNDAA SSYN D_RF_AG UNR_SDA _FA- _XALO _XAL _RS#

28 SQUMAS LÉROS Placa Principal L(A)W M OU FAUL LM N N LOS O M L0 N/0 0 N/0U 0 N/U N/ N/ N/ N/ 9 N/ L0 N/0 N/ 0 N/0U N/ N/ N/ U0 N/PS0 L0 N/ 0 N/00U V N/ _GPO R00 N/ _V R N/0 R N/0K R N/0 0 N/ N/0K R9 R0 N/K R N/00K +V N/ N/ R N/0K 00 N/U N/0K R AVDDV AVDDV _DV _DV _AV _V _DV _GPO9

29 9 SQUMAS LÉROS Placa Principal L(A)W M close O M LOS O PMA N/0P N/R R N/R R N/R R N/R R N/R R N/R R N/R R N/R R0 N/R R9 N/R R N/R R 09 N/0P N/R R N/R R N/R R N/R R9 N/R R0 N/R R N/R R N/R R N/R R N/R R N/R R M OULK M OUDAA M OUDAA M OUDAA M OUDAA M OUDAA M OUDAA M OUDAA M OUDAA0 M OUSYN M OUVALD M NLK M NDAA M NDAA M NDAA M NDAA M NDAA M NDAA M NDAA M NDAA0 M NSYN M NVALD _NSYN _NVALD _NLK _OULK _OUSYN _OUVALD _OUDAA _OUDAA _OUDAA _OUDAA _OUDAA _OUDAA _OUDAA _OUDAA0 _NDAA _NDAA _NDAA _NDAA0 _NDAA _NDAA _NDAA _NDAA

30 0 SQUMAS LÉROS Placa Principal L(A)W M LOS O M9 LOS O M N/ R R N/ R N/ P00 0 N/0P 9 N/0P R9 N/ N/ R0 N/0P N/0P N/0P _## _OULK _OUSYN _DV _O## _W# _# _OWR# _NSYN _NDAA0 _OUVALD _A _NDAA _D _D# _A _D# _D _A0 _ORD## _RQ# _OUDAA _WA# _NDAA _D0 _D _NLK _A _NDAA _OUDAA _VS# _D _D _# _A _NDAA _A _A _OWR## _OUDAA0 _NDAA _OUDAA _A _OUDAA _OUDAA _RS _NVALD _NDAA _OUDAA _A _A _OUDAA _NDAA _A9 _A _ORD# _V _RG# _O# _W## _A0 _V _V _V _A _A _D _D

31 SQUMAS LÉROS Placa Principal L(A)W FLASH/DDR/JAG DU V DU S DU DU W DU VSS DU DU DU Q HOLD D Serial Flash HOLD#_F V_FLASH PDD_F POO#_F PDD_F F_S FLASH_WP R0 N/ R9 N/ R99 N/0K GPO_ R0 DVDDV PDD PDD_FLASH R U00 N/MP DVDDV L00 0 R0 K R0 K DVDDV PO# PO0# POO# PDD NOR_S# FLASH_WP#

32 SQUMAS LÉROS Placa Principal L(A)W S/SO0 SLK SO V WP#/SO SO/SO S#.V.V(9V).9V(V) RS circuit System Reset# RS_V R N/K R K V V_FLASH F_DA F_WP R N/K R K R R F_DA0 F_SL U0 MXL R 0K R 0K R R PDD POO# R0 K VS Q0 90 0U R9 K Q0 90 R K R 00K R 0 Q0 90 Z R 0K R 0K 0P R9 K OPRL0 ORS# NOR_S# FLASH_WP# V_FLASH PDD_FLASH

33 SQUMAS LÉROS Placa Principal L(A)W FLASH/DDR/JAG A0 A A A A A A A A A9 A0 A A DQU0 DQU DQU DQU DQU DQU DQU DQU DQSU /DQSU DMU DQL0 DQL DQL DQL DQL DQL DQL DQL DQSL /DQSL DML A0 A A /S /RAS /AS /W K /K K OD /RS VRFA VRFDQ ZQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS9 VSS0 N N N N N N N VSS N P P N P P R R R L R N D A A A D F F F H H G H F G M N M L J K L J K K9 K M H L A A 9 D 9 F H H9 9 D D F9 G G9 D9 G K K N N9 R R9 A9 G J J M M9 P P9 9 J J9 L L9 M U0 HQGFR R 0 N/0U 0 0U K/% R DDRV DDRV DDRV K/% R R K/% DDRV 0 R K/% _A _RS# _OD _K LK0# LK0 _W# _AS# _RAS# _S# _A _A _A0 RDQM0 RDQS0# RDQS0 RDQ RDQ RDQ RDQ RDQ RDQ RDQ RDQ0 RDQM RDQS# RDQS RDQ RDQ RDQ RDQ RDQ RDQ0 RDQ9 RDQ _A _A _A0 _A9 _A _A _A _A _A _A _A _A _A0 RVRF RVRF ZQ

34 SQUMAS LÉROS Placa Principal L(A)W FLASH/DDR/JAG SDA SL W V VSS /N /N 0/N ADDRSS "A0" SYSM PROM S_V S_W Q00 90 _SL _DA R N/R R0 0K R0 K R K _A _A R0 0 _A0 _A0 R 0 _S# _S# R 0 _OD _OD R 0 0 R R0 0 R0 R0 _A _A _A _A _K _A0 _A _A _A _A _A _A _A0 _A _A9 _RS# 0 R _A _RAS# _AS# _W# _A _A _A _A _K _A0 _A _A _A _A _A _A _A _RAS# _AS# _W# R 0 0 R0 0 R9 0 U0 MMN R K 0 0P 09 0P 0 DVDDV DVDDV OSDA0 OSL0 LK0 LK0# RLK0 RLK0# _A _RS# _A9 _A0 R 0K GPO_

35 SQUMAS LÉROS Placa Principal L(A)W RS&MU RU DGAL AS0 AMP L0 VALU R990 N/ R99 N/ MAN_POWR D0 LL D0 LL 0 U 09 U 0 U L0 R 0K U V R K R 0K Q 90 R K Q0 90 R0 K V V DVDDV AMP_V MAN_POWR R 0 R9 R R R R R 00P 00P 00P L R R U V V R 0K R 0K R K Q09 90 R K L 00P R9 K AMP_RS OPRL AMLK ALK ALRLK AOSDAA0 AOLRK AOLK AOMLK ASDAA0 MU

36 SQUMAS LÉROS Placa Principal L(A)W P_A P_A OU_ PVDD_ PVDD_ S_ S_ PVDD_ PVDD_ OU_ P_D P_D OU_D PVDD_D PVDD_D S_D GVDD_OU VRG A DVSS DVDD SS RS SL SDA SDN SLK LRLK PDN VR_DG DVSSO OS_RS MLK FAUL AVDD PLL_FLP PLL_FLM AVSS N O_ADJ SSMR GVDD_OU S_A PVDD_A PVDD_A OU_A VR_ANA R- L- R+ L+ R0 N/ 0.0U 0.0U U R R 0.0U N/0P N/0P N/0P N/0P 0U V L+ L- R_ R+ AVSS U0 AS0 R R 0 0.U L00 UH MU VR_DG R 0.0U 0.0U 00P 00P L0 0 V R9 N/ R9 N/ R N/ U 9 0P R K P0 V R 0K V R0 K R9 K L AVSS 0 U 0 U R0 0 R R R R 0 L0 UH AMP_V AMP_V R 9 00P L0 UH 0 0.0U AMP_V AMP_V U L 0 0.0U 0 0.U 0.0U R9 R L0 UH 0.0U 0 U 0P FAUL ASDAA0 ALK ALRLK AMLK FAUL VR_DG OSDA0 OSL0 AMP_RS SPK_L+ SPK_L- SPK_R+/SU+ SPK_R-/SU- V 0U

37 SQUMAS LÉROS Placa Principal L(A)W Y0 Y Z Y Y V VSS A A0 YA Y0A ZA YA YA VDD R99 K R99 K R K R K 99 N/U V R K K R 9 0U 0 N/U V M99 0U 0 R9 9 0 U00 HF0 9 0P 9 U 90 U R K R K R0 K R R K R R 0K +V Q0 90 +V R K R N/0K R N/0K R R 0P R R K R0 R9 0K +V Q0 90 OPRL MUX_LA MUX_L OPRL AN0_L_AAD AN0_R_AAD AN_L0 AN_R0 YPPR_L_N SAR_R_N MUX_L AN_L0 YPPR_R_N AN_R0 VGA_R_N VGA_L_N SAR_L_N MUX_LA AV_R_N AV_L_N

38 SQUMAS LÉROS Placa Principal L(A)W N+ N- OU V+ N+ N- OU V- SAR Audio Output D00 N/0V 0P 0P P P R0 K R0 K R0 K R0 K U U R K R K L0 R0 K R09 K U0 AZ R00 R 0 0U 9 U U L0 0U 0 R0 K R0 K R0 R0 AL0O AR0O SARL_PA V SARR_PA NAR M0 HeadPhone and SAR MU R 0K GPO_ 00 U Q0 N/90 Q0 N/90 R N/K R N/K Q0 N/90 R9 N/0K PHON_MU R K HP_V R9 K Q 90 Q 90 R K R90 K VS R9 0K VS Q0 90 SARL_PA SARR_PA

39 9 SQUMAS LÉROS Placa Principal L(A)W Y/AV P/R PR/L AV L DFAUL H headphone out 0.0U 0 0.0U R9 K R9 K R99 0K R9 0K R 0K R9 0K 9 0P 9 0P R9 K R K 9 000P 9 000P Q0 Q9 Q Q R9 R R9 R R9 R R99 R U 9 U 9 R K R9 K R K R K R K R K V U U V HP_V R N/U 9 N/U PHON_R PHON_L L 0 00P HP_V V PHON_MU Q0 90 R9 0K R90 K Q 90 DVDDV Q 90 Q00 90 Q0 90 L0 L09 Z0 R 0K R P00 Z00 ARO HP_V R9 K U R9 0K R9 K Q 90 N/0.0U N/0.0U R 0K L 0 L 0UH L 0UH R 0K 0 00P U 9 R9 K PHON_R PHON_L GPO_ PHON_R PHON_MU ALO HP_V

40 SQUMAS LÉROS Placa Principal L(A)W LVDS OU OSDA0 R90 N/ Z90 9 N/0P Z9 VR_X R9 N/ Z9 VR_X LVDSX_AO0P LVDSX_AOP LVDSX_AOP LVDSX_AOKP LVDSX_AOP LVDSX_AOP DR LVDSX_A0P LVDSX_AP LVDSX_AP LVDSX_AKP P LVDSX_AO0N LVDSX_AON LVDSX_AON LVDSX_AOKN LVDSX_AON LVDSX_AON _SL LVDSX_A0N LVDSX_AN PANL_DM LVDSX_AN LVDSX_AKN PANL_DM Z90 LVDS_FORMA R90 N/ Z90 Z90 OSL0 R909 N/ 9 N/0P L9 X_AO0N X X_AO0P L90 X X_AON X_AOP L90 X X_AON X_AOP L90 X X_AOKN X_AOKP L90 X X_AON X_AOP LVDSX_AO0N 9 LVDSX_AO0P 9 LVDSX_AON 90 LVDSX_AOP9 LVDSX_AON 9 LVDSX_AOP 99 LVDSX_AOKN9 LVDSX_AOKP9 LVDSX_AON9 LVDSX_AOP9 N/0P N/0P N/0P N/0P N/0P N/0P N/0P N/0P N/0P N/0P LVDSX_AP LVDSX_AP R LVDSX_AN LVDSX_AN L90 X X_AON X_AOP LVDSX_AON90 LVDSX_AOP90 N/0P N/0P Z999 DVDDV LVDSVDD 90 L90 X_A0N X X_A0P L90 X_AN X X_AP L9 X_AN X X_AP LVDSX_A0N9 LVDSX_A0P 9 LVDSX_AN 90 LVDSX_AP9 LVDSX_AN90 LVDSX_AP909 N/0P N/0P N/0P N/0P N/0P N/0P GPO_ GPO_ R9 N/0K R9 N/ R9 N/ R9 N/ R9 N/K R90 N/ R9 N/K LVDS_FORMA _SL R99 DR L90 X X_AKN X_AKP L909 X_AN X X_AP L90 X_AN X X_AP LVDSX_AKN 90 LVDSX_AKP 90 LVDSX_AN9 LVDSX_AP9 LVDSX_AN90 LVDSX_AP90 N/0P N/0P N/0P N/0P N/0P N/0P 0

41 SQUMAS LÉROS Placa Principal L(A)W LVDS POWR L9 N/0 V Z9 L9 N/0 LVDSV L9 0 L9 0 V 9 N/0U 9 LVDS OU R90 K 90 N/ Q90 PMVXP S G D LVDSVDD U LO = > LVDS POWR OFF H = > LVDS POWR ON R90 R90 0K LVDS_PWR_N R9 0K R90 0K 9 R9 K Q LVDS

42 SQUMAS LÉROS Placa Principal L(A)W LVDS R/KY D ONNOR L9 0 _ L_SNSOR LD_R LOGO _V K_+V _K L9 N/0 0 R99 L9 N/0 R R_POW KY_POW KY L99 0 L9 0 L9 0 L9 0 L90 0 L9 0 KY R900 N/VA R9 0K R9 00K 9 P90 P900 VS L P P P P 9 F P OR_OU ADN_SRV PWM_LOGO&LD_ GPO_ GPO_ LD_R R VS OPRL +V VS +V L_SNSOR OPRL

43 SQUMAS LÉROS Placa Demoduladora L(A)W DVDDV R0 /N R 0K R /N R 0K D DVDDV XSL XSL0 R9 K R0 K R 0K R 0K D SLADRS0 SLADRS DVDDV R 0K FA+_D FA-_D ADQ_AP ADQ_AN SMD0 AG S_NFO K DLK SMD SL_D SDA_D XSL XSL0 XO_D X_D SL SDA XSL XSL0 X0 X PLLVDD ADVDD 0 9 AD_AP AD_AN ADQ_AP ADQ_AN SMD0 AG S_NFO 9 K 0 DLK DM SMD 9 0 AVDDV_ AVDDV_ AD_VRFP AD_VRFN AD_VRF DVDDV_ DVDDV_ VRVDD AD_DVDD PLLVSS AD_AVSS DVDDV_ VDD VDD VDD VDD U VSS 90FG DRVDD DRVDD VSS AD_VSS DVDDV_ VDD VDDS VSS VSS VSS VSS VSS 0 DVDDV_ 9 VDDS VDDS SRD RLOK RRR SLOK SSFLG0 SSFLG SLADRS0 SLADRS SRK PVAL SY RSORF VSS VSS9 NSL NSDA AGN AGNR FL SYRSN DAA RLOK RRR SLOK SSFLG0 SSFLG SLADRS0 SLADRS LK VAL SY RSORF NSL NSDA AGN AGNR FL SYRSN LK_N DAA_N 9P 9P R 0 R 0 SL_D SDA_D AD_VRFP AD_VRFN AD_VRF A D D P X.M R K P R M X_D XO_D FL 00P AD_VRFP AD_VRFN AD_VRF /N ADQ_AP /N ADQ_AN 9 SMD0 AG S_NFO K DLK SMD R 0K R 0K R 0K R 0K R9 0K R0 0K A A NAR A D NAR

44 SQUMAS LÉROS Placa Demoduladora L(A)W D A D D /ADJ OU VN N OU L U U AP0 U LDS DVDDV 9 00U V 9 00U V DVDDV DVDDV DVDDV AVDDV DVDDV DVDDV U 0 L 00U V R9 DVDDV 9P/N R L 0.UH/N L 0.UH/N 9P/N 9P/N L N/0.UH R 0 FA+_D FA+ FA-_D FA-

45 SQUMAS LÉROS Placa Demoduladora L(A)W DVDDV DVDDV R K L DVDDV_ DVDDV L DVDDV_ RSORF R 0K D Q 90 DVDDV D 9 0 U D U 9 D L DVDDV_ DVDDV U L DVDDV_ 9 U 0 RLOK RRR R 0K/N R 0K/N D SLOK R 0K/N SSFLG0 SSFLG R 0K/N R 0K/N NAR AVDDV AVDDV L D A U AVDDV_ DVDDV L D U DVDDV_ L AVDDV_ 9 U 000P D A

46 SQUMAS LÉROS Placa Demoduladora L(A)W D AGN R K A F_AG SYRSN R DVDDV R K DMOD_RS 9 0P 9 0P R9 R R9 R R R 0P R9 R 9 0P S_SYN S_D0 S_LK S_VALD L L L0 L P R 0K/N 9 0U/N D SY DAA LK VAL L L9 D L L L L /N L9 /N L0 /N A P90_ D SD0 SVAL SSYN S_D0 0 S_VALD S_SYN LK_N D UNR_LK P90 SLK 9 S_LK D DMOD_RS DAA_N D UNR_DAA DMOD_RS D D D F_AG F_AG FA- FA- 0 FA+ FA+ P900 NSDA NSL P900_ NSL NSDA D 9 D DVDDV DVDDV

47 SQUMAS LÉROS Placa Principal L/0 H = > POWR_OFF LO = > POWR_ON ack Light control DMMNG MAN_POWR +V R K R9 R90 D0 N/LL L_DMMNG PAN_ON/OFF 0 U R K9 R0 K R ON/OFF_PWR ON/OFF_PWR R AUDO_PWR PANL_DM PANL_DM S_POWR S_POWR PAN_ON/OFF MAN_POWR MAN_POWR AUDO_PWR 0 9 P00 R N/ R N/K Q0 90 R 0K R K R 0K Q0 90 R 0K R0 K +V VS DVDDV ADN_SRV VR_X PANL_DM PAN_ON/OFF S N SW OMP F SS N close to P00 L0 0 U0 MP VK L00 UH R K PAN_ON/OFF 0 0U V 00U V R9 K 0 U 00P 0.0U V VK R0 0K R 00K 0 9 0P ON/OFF_PWR S_POWR MAN_POWR PANL_DM POWR

48 SQUMAS LÉROS Placa Principal L/0 D DA G G S D DA S N OU U Q0 N/90 U0 N/R9- Q0 N/A00 VS R N/K AUDO_PWR R K R 0 Q0 90 V N/ R N/K N/0K R R N/K R R0 N/ V M_V R0 N/ R0 N/ R0 N/ N/ R0 N/ N/ R N/K N/U R N/ N/0K R R 0K R 0K S_POWR VS S_POWR VS ON/OFF_PWR OPWRS S_POWR MAN_POWR S_POWR ON/OFF_PWR ON/OFF POWR

49 9 SQUMAS LÉROS Placa Principal L/0 V LGA PHAS OO F UGA VN D DA G G S D DA S /ADJ OU VN VOU VN ADJ/ S N SW OMP F SS N /ADJ OU VN Vout=0.*(0+00)/0=.0 AVDDV U00_V 0U V R9 L0 UH L0 N/0UH 0 L L0 0 0 L L 0 L0 UH R9 R9 DVDDV DVDDV AVDDV AVDDV AS-. U0 R0 +V U0_AVDDV U00 MP9DN U09 AZ0 U0 ASAD 0 00U V 00U V AVDDV Q00 DN0L 00U V V 0U 00 0U V 00U V L 0 0.0U 0.0U 0U V 0 U 0 U 0 0U 9 R9 R9 R9 R R R R00 +V 00P M_V U0 R0 N/0 L00 N/0 L09 V N/00P N/ 09 U +V +V R K R +/-% U R K % R 0K % SR D00 K R 00P U 0 MAN_POWR 9 D0 LL MAN_POWR V V M_V POWR

50 0 SQUMAS LÉROS Placa Principal L/0 VOU VN ADJ/ VOU VN ADJ/ /ADJ OU VN POWR R0 R R9 R R R 0 00U V R9 U0 AS- U AZ0 U N/AZ R /% V 0U UNR_V 00U V V_ R99 R N/R V +V_D +V +V_D DDRV V_ R R UNR_V DDRV

51 SQUMAS LÉROS Placa Principal L/0 UNR/DMOD D SDA DF+ + AF RF-AG N N AS SL F_AG DF- AMP_ turner_ R0 0 R U V + 0 N/0.0U R0 N/0K 0 9 U00 R0 R0 + _FA- _FA+ RF_AG UNR_F_AG AS R09 /N _SDA L09 UNR_FA- UNR_FA+ _SDA _SL 0 0P 09 0P UNR_V U UNR_DAA UNR_LOK RF_AG _SL UNR_RF_AG

52 SQUMAS LÉROS Placa Principal L/0 close to tuner close to 0L R0 N/0 N/0 R00 R9 R9 R K R K R9 R99 L 0.UH 9 N/P 9 N/P 09 N/P N/P N/P N/P 9 N/P 0 N/P P P 0 0.0U FA_N- L00 R L0 R L 0 L9 0 FA-_D FA_N U FA+_D UNR_FA+ UNR_FA- FA-_D 0K R L9 N/0.UH 0.0U F_AG R0 0 R N/P UNR_DAA UNR_LOK UNR_F_AG F_AG FA+_D DMOD_FA+ DMOD_FA- 0 0P 9 0P UNR_V UNR_SL UNR_SDA OSL0 OSDA0 UNR/DMOD D

53 SQUMAS LÉROS Placa Principal L/0 V S A lose to tunter R R R9 N/ Q0 N/90 A_RF_AG U0 N/LVG RF_AG D_F_AG_ 90 N/0.0U Q0 N/90 R9 N/K R9 N/0K R9 N/0K V AOSDAA 00 N/0U N/ UNR_V AOSDAA F_AG A_F_AG UNR_V UNR/DMOD D

54 SQUMAS LÉROS Placa Principal L/0 HDM SDA SL WP V A A A0 RX+ RX- RX+ RX- RX0+ RX0- RX+ RX- N N DDLK DDDA V HPD RX+ RX- RX+ RX- RX0+ RX0- RX+ RX- N N DDLK DDDA V HPD SDA SL WP V A A A0 H:WP,L:WR H:WP,L:WR HDM_DD HDM_DD HDM HDM R0 K R K R K R K U0 N/A P P0 0 N/ N/ R N/0K R N/0K U0 N/A0 DDSDA RXLKN RXLKP RX0N RX0P RXN RXP RXN RXP RXLKN RXLKP RX0N RX0P RXN RXP RXN RXP HDM_SDA HDM_SL WP HDM_V HDM_V HOPLUG HDM_V WP HDM_SDA HDM_SL HOPLUG HDM_V HDM_V R N/K R K R 00K R N/K HDM_V R0 K Q0 90 R K R 00K Q R R 0 R0 K K R9 DDSL HDM K R0 DDSL DDSDA R 0 0 R DDSL DDSDA HDM DDSDA DDSL HDM_AR

55 SQUMAS LÉROS Placa Principal L/0 HDM RX+ RX- RX+ RX- RX0+ RX0- RX+ RX- N N DDLK DDDA V HPD SDA SL WP V A A A0 H:WP,L:WR HDM HDM_DD R K R K U0 N/A P0 N/ R N/0K RX0N RX0P RXN RXP RXP HDM_SDA HDM_SL WP HDM_V HDM_V HOPLUG HDM_V HDM RXLKP RXLKN R9 N/K Q0 90 R K R0 00K DDSL K R0 R0 K R0 0 0 R9 DDSDA DDSL DDSDA RXN V A O Y HDM_AR R N/0K R0 0 AVDDV GPO_0 R U0 LVGGW U R9 K R K R R R R R 0K M0L_SPDF +V HDM_AR

56 SQUMAS LÉROS Placa Principal L/0 HDM SL_SNK SDA_SNK POW_SNK HPD SDA SL Z V X Y Z Z HPD_SNK Y Z _RS A POW A A HPD POW A POW V A A SL RX POWDN SDA_L SL_L _ADDR Y Y SL SDA A A V A V HPD N A SDA A A RXLKN DDSL N/ L00 L99 RXLKP RXN RXP RXN RXP RXN RXP RXN RX0P RX0N RXLKP RXLKN HDM_V DDSL DDSDA HOPLUG DDSDA K R HDM_V HOPLUG RXP RX0P RX0N VS VS 0 U V_HDM RXN RXP HOPLUG HDM_V K R V_HDM V_HDM K R V_HDM N/ R N/.K R R R0 R9 M_RX_ M_RX_ M_RX_ M_RX_ M_RX_0 M_RX_0 HDM_ R 0 HDM V_HDM D00 LL R K R K V_HDM R K U 0 AVDDV R R R R OSDA0 OSL0 P 0 0 P M_RX_ M_RX_ V_HDM HDM_SL HDM_SDA K R 90 Q00 K R HDM_HPD R K K R V_HDM DDSDA DDSL RXN RX0N RXLKN RXP RX0P RXLKP U00 PS

57 SQUMAS LÉROS Placa Principal L/0 LAK V VN X LD DRV GRN LU RD WH RD YPPR N close to YPbPr connector close to M0 SPDF OU Near onnector SPDF(compatible with P0) Z0 _SPDF P0_ 9 0 P0 L L L L0 L0 R0 N/ R0 0 P P0 M0L_SPDF +V R99 VA P0_S 99 N/P P PR_N PR_N R N/0 Y_N_ P_N_ P_N RD YRR_N YRR_N R90 N/0 R9 N/0 YRR_N YRL_N PR_N_ F00 F9 P R 0 R F R 0K R 0K R0 K P P R 0 R 0 R 0 R 0 F R R R R R R R R9 R 0 00P 9 0.0U 0.0U 0.0U 0.0U 0 U 0 U 0P R R 0 0P R R F F R K YPPR_R_N PRP YPPR_L_N SOY YP PP OM P_N P_N PR_N_ Y_N Y_N OMX YRL_N YRL_N Y_N_ WH RD YLLOW WH RD YLLOW YPbPr_ M0_ AV_R SDAV_R SDAV_L SDAV_V SDAV_AUL_N AV_L AV_V R0 R0 P P AV_V_N AV_AUR_N AV_AUL_N SDAV_AUR_N SDAV_V YPPR/US/SAR/SPDF

58 SQUMAS LÉROS Placa Principal L/0 VGA ONNOR close to M0 close to VGA connector Q0 N/Z R N/0K R99 N/K R N/0K R N/0K Q0 N/Z Q0 N/Z R9 0 R N/0 R N/0K R N/0 R9 0 L L L F F R9 N/VA R9 N/VA VGA_RXD VSYN_N V_N RD R0 N/VA F0 VGA_XD VS H_N VGA_PLGP R00 N/VA LU R0 N/VA F00 RD VGASDA_N VGASDA_N GRN GRN HSYN_N LU VGA_RXD VGASL_N VGA_XD 0 9 P0 GPO_ R0 N/VA R0 N/VA R 0.0U R R R R 0 0P 9 0.0U R R 0P R R0 0P 0.0U 0 R9 R R 0.0U 00P R R 0P 0P VGA_PLUGPWR VGA_PLUGPWR R 0K R0 0K F0 F0 F0 R 0 R 0 VGASL VGASDA VGASDA_N VGASL_N RP SOG GP P GRN VGAOM VGASL_N U0X UX VGA_RXD VGA_XD VGA_PLUGPWR RD LU YPPR/US/SAR/SPDF

59 9 SQUMAS LÉROS Placa Principal L/0 V- DNG- DPOS- - MN-HOL MN-HOL V- DNG- DPOS- - MN-HOL MN-HOL US POR 0 US POR 0 00U V F US_DP US_DP0 US_DM0 US_DM0 +V_US +V_US _P _P0 F R0 R R00 R P P0 L0 F +V F0 R R R R US_DM0 US_DP0 US_DM US_DP AUDO NPU AV_AUR_N AV_AUL_N SDAV_L_N F F L9 L 0P 0P 0 U 9 U R009 K R00 K R00 0K R00 0K L0 L0 R 0K R 0K R K R K 0 U 0 U 0P F 0P F09 SAR_R_N SAR_L_N SDAV_AUL_N SDAV_AUR_N SDAV_R_N YPPR/US/SAR/SPDF

60 0 SQUMAS LÉROS Placa Principal L/0 S R WH RD YLLOW NARLY ONNOR VS OU AUDO OU VGA AUDO NPU NARLY AUDOOU_R AUDOOU_L P0 P P _AVOU AV_OU VGA_RN VGA_LN S_AV_OU _P00 VGA_AUDO_R_N VGA_AUDO_L_N P R L0.UH N/P R9 R L00 L P00 R9 N/K R N/K N/VA R N/VA R R N/VA 0P 0P L0 0 L0 0 F F F0 N/VA R0 R0 N/VA R 0K R 0K R K R K R R 0 U 0 U F0 F0 0P 0 0P F0 0P 0P F SARL_PA VS_OU SARR_PA VGA_L_N VGA_R_N HSYN VSYN HSYN_N VSYN_N S_AUR_OU S_AUL_OU VS/RG N NARLY ONNOR NARLY R 0 VS_OM F0 0P 0.0U R00 N/VA R00 R R00 R00 0 R R0 N/VA AV_V_N R 0 0.0U R R 0P F VSP 0.0U SDAV_V VSP YPPR/US/SAR/SPDF

61 SQUMAS LÉROS Placa Principal L/0 M0 FSR_WR GPO VO_ AVDD_VPLL AP AN AP AN AP AN AKP AKN AP AN AP AN A0P A0N AVDD_LVDSA AVDD_LVDSA AOP AON AOP AON AOP AON AOKP AOKN AOP AON AOP AON AO0P AO0N VK VK VK AVDD_MMPLL AVSS_MMPLL ROD/RK RA/RA0 RA/RA RA/RA RA/RA RA/RA RA0/RA RA/RA RAS/RA RS_/RRAS_ RRAS_/RAS_ RA9/RW_ VO_ RA/RA0 RA/RA RA/RA9 N/RRS_ RA/RA RA/RA RA0/RA RA/RA RA0/RA RA/RA0 RW_/RS_ RK/ROD GPO GPO GPO GPO GPO GPO GPO GPO0 GPO GPO GPO0 VO_ VK PGO POW_ PAAL PAL PO_ PAR_ POO_ PO0_ PDD VO_ PDD PDD PDD PDD PDD PDD PDD0 _N SP_L SP_DAA SP_LK VK VO_ DMOD_SDAA0 DMOD_SSYN DMOD_SVAL DMOD_SLK OSDA OSL DMOD_RS RF_AG F_AG AOLRK AOSDAA0 AOMLK AOK AOSDAA ASPDF VK VK0 AR_ADA AR0_ADA AL_ADA AL0_ADA AVSS_DA AVDD_DA AVDD_AAD ANO_L_AAD VMD_AAD AN0_R_AAD LOUP VK RVRF RDQ/RDQ RDQ/RDQ JK JMS JD VO_ RDQ/RDQ RDQ/RDQ0 RDQ/RDQ RDQ9/RDQ9 VO_ RDQ/RDQ RDQ/RDQ RDQM/RDQM VK RDQS0/RDQS0 RDQSO_/RDQS0_ RDQM0/RDQM0 VO_ RDQS/RDQS RDQS_/RDQS_ RDQ/RDQ RDQ/RDQ VO_ RDQ0/RDQ0 RDQ/RDQ RDQ/RDQ RDQ0/RDQ VO_ RDQ/RDQ RDQ/RDQ VO_ RLK0/RLK0 RLK0_/RLK0_ VK JDO JRS_ OPWM0 ORS_ PWRV HDM_HPD HDM_SL HDM_SDA HDM_ AVDD_HDM RX_ RX_ RX_ RX_ RX_0 RX_0 RX_ RX_ AVDD_HDM US_P_VR AVDD_US_P US_P_DP0 US_P_DM0 US_P_DP US_P_DM VK VO_ AVDD_XAL_S XAL XALO AVDD_DMOD AVSS_DMOD AVSS_DMOD AVDD_FPGA ADNN_DMOD ADP_DMOD AVDD_DMOD AVDD_VS VS0P VS_OM VSP SY0 S0 SY S AVDD_PLL VK9 FS_VDA AVDD_VDA VDA_OU VDA_OU AVSS_RG AVDD_RG PR0P P0P OM0 Y0P SOY0 PRP PP OM YP SOY RP OM GP SOG P HSYN VSYN AVDD_VGA_S AVDD0_LDO ADN_SRV ADN_SRV ADN_SRV ADN_SRV ADN0_SRV VK VGA_SL VGA_SDA OPWRS OPRL OPRL0 OR U0X UX AVDD_PDM_S OPRL OPRL OPRL OPRL PAD_ FLASH AUDO LVDS OU _S N HDM* US* JAG VGA YPPR/DVD SAR/YPPR S_VS/AV SAR/AV Analog F N DDR R N/0K R N/0K R0 0K JDO JK JMS JD R K AVDD0_LDO 0 N/U V MU_RS M0L_RF_AG R R R0 0K 9 0.0U N/000P R N/00K AVDD_DA ADN_SRV M_RX_ R09 K M0L_F_AG R 00K U00 M0 R 0K R R 0 0.0U DDRV R0 % R0 K % R00 K % R0 K U 0P 0P AVDDV SDA0 OSDA0 A_RF_AG SL0 OSL0 A_F_AG OPRL OPRL OPRL OPRL VS UX U0X OPRL0 OPRL OPWRS VGASDA VGASL VK SAR_FS0 ADN_SRV KY VS_ VSYN HSYN P SOG GP VGAOM RP SOY YP OM PP PRP SOY0 Y0P OM0 P0P PR0P AVDDV_ UNR_YPASS_OU MONOR_OU AVDDV VK AVDDV VSP S0 SY0 S VS_OM VSP AVDDV_ AVDDV_ FA_N+ FA_N- AVDDV_ AVDDV_ OXALO OXAL VS DVDDV VK US_DM US_DP US_DM0 US_DP0 AVDDV AVDDV_ M_RX_ M_RX_0 M_RX_0 M_RX_ M_RX_ M_RX_ M_RX_ AVDDV_ HDM_ HDM_SDA HDM_SL HDM_HPD PWRV L_DMMNG JDO VK RLK0# RLK0 DDRV RDQ RDQ DDRV RDQ RDQ RDQ RDQ0 DDRV RDQ RDQ RDQS# RDQS DDRV RDQM0 RDQS0# RDQS0 VK RDQM RDQ RDQ DDRV RDQ9 RDQ RDQ0 RDQ DDRV JD JMS JK RDQ RDQ VK AN0_R_AAD AN0_L_AAD AVDDV_ AVDD_DA AL0O ALO AR0O ARO VK M0L_SPDF AOSDAA AOLK AOMLK AOSDAA0 AOLRK DMOD_RS SL0 SDA0 S_LK_N S_VALD_N S_SYN_N S_D0_N DVDDV VK SP_LK SP_DAA SP_L _N# PDD0 PDD PDD PDD PDD PDD PDD DVDDV PDD PO0# POO# PAR# PO# PAL PAAL POW# GPO_ VK DVDDV GPO_0 GPO_ GPO_ GPO_0 GPO_ GPO_ GPO_ GPO_ GPO_ GPO_ GPO OD _S# _A0 _A _A _A _A _A _RS# _A9 _A _A0 DDRV _W# _AS# _RAS# _A _A _A _A _A _A _A _A0 _K AVDDV VK X_AO0N X_AO0P X_AON X_AOP X_AON X_AOP X_AOKN X_AOKP X_AON X_AOP X_AON X_AOP X_AON X_AOP AVDDV X_A0N X_A0P X_AN X_AP X_AN X_AP X_AKN X_AKP X_AN X_AP X_AN X_AP X_AN X_AP DVDDV LVDS_PWR_N VMD_AAD RVRF JRS# US_VR ORS# VDA_FS ADN_SRV OR_OU AVDDV

62 SQUMAS LÉROS Placa Principal L/0 DDRV DDR O POWR(close to chip) DDRV 09 0U V 0 U U.V O POWR(close to chip) DVDDV VK core power(close to chip) DVDDV VK 0 U 0 0U V 0 U M0

63 SQUMAS LÉROS Placa Principal L/0 M0 opctrl AOSDAA opctrl SRAPPNG strapping mode+m+serial boot ROM boot+m mode+m+serial boot ROM boot+m R K R R R R0 R9 R R R R VS R U OXALO R0 N/M R0 R0 N/ R N/K R N/K R N/K VS_ AVDDV R9 K R0 K R0 K AVDDV_ AVDDV_ AVDDV_ AVDDV_ AVDDV_ AVDDV_ P X00 M P DVDDV VS MONOR_OU VS_OU AVDD0_LDO OXAL OPRL OPRL AOSDAA UNR_YPASS_OU AVDDV AVDDV_ AVDDV_ VS

64 SQUMAS LÉROS Placa Principal L/0 VS VS Standby power lose to pin of U VS_ 0 U AVDDV AVDDV AVDDV_ AVDDV_ AVDDV_ 00 U 0 lose to pin of U AVDDV AVDDV AVDDV_ AVDDV_ AVDDV_ AVDDV_ AVDDV_ 0 U 9 lose to pin of U M0

65 SQUMAS LÉROS Placa Principal L/0 D D D D VDDS VDDS VDD VDDS DRVDD DRVDD VDD VDD VDD VDD SRD SLOK RRR SSFLG0 SSFLG SLADRS0 SLADRS SRK PVAL NSL NSDA VSS9 VSS VSS VSS VSS VSS ADQ_AN AD_AP AD_AN S_NFO AG DLK K SMD DM SL SDA VSS X X0 XSL0 XSL SMD0 ADQ_AP AD_VRFP AD_VRFN AD_VRF PLLVSS AD_AVSS AD_VSS VSS VSS SYRSN FL AGNR AGN RSORF SY RLOK PLLVDD ADVDD VRVDD AD_DVDD DMOV DMOV DMOV L09 0 R 0K R 0K R /N R0 /N U0 90FG 9P 9P SLADRS SLADRS0 UNR_SDA R 0 R 0 OSDA0 OSL0 LK DAA SY VAL RSORF RRR SLOK SYRSN SSFLG0 R 0K DLK SMD SL_D SDA_D SL_D SDA_D X_D XO_D XSL0 FA-_D_ FA+_D_ UNR_SL AGN S_NFO SLADRS R 0K AD_VRF AD_VRFN AD_VRFP FL DVDDV_ DVDDV_ AVDDV_ AVDDV_ DVDDV_ DVDDV_ DVDDV_ ADQ_AN ADQ_AP XSL SMD0 R 0K SLADRS0 AG K AGNR R0 K R9 K SSFLG RLOK XSL XSL0 AVDDV

66 SQUMAS LÉROS Placa Principal L/0 P X0.M R K P X_D XO_D 00P AD_VRFP AD_VRFN 9 AD_VRF N/ ADQ_AP N/ ADQ_AN AGN D_F_AG_ NAR D NAR D DMOV 9 0P 9 0P 0P 9 0P S_SYN_N S_D0_N S_LK_N SYRSN P R R 0K/N DMOD_RS 9 0U/N R9 R R9 R R R R R9 S_VALD_N D SY DAA L L L0 L0 LK R M VAL FL SMD0 AG S_NFO K DLK SMD R 0K R 0K R 0K R 0K R9 0K R0 0K R K R K

67 SQUMAS LÉROS Placa Principal L/0 D D D N OU /ADJ OU VN D 9 00U V 0 N/9P N/9P L N/0.UH L N/0.UH N/9P L N/ DMOV DMOV DVDDV DVDDV U 0 0 L L9 L L L AVDDV DMOD_FA+ DMOD_FA- U0 LDS U0 AP0 L0 /N L9 /N L /N L 00U V R9 0 L N/0.UH R L 0 00U V U L0 0 AVDDV DVDDV DVDDV DVDDV R FA+_D_ FA-_D_

68 SQUMAS LÉROS Placa Principal L/0 M0 D D D D D D D NAR DMOV DMOV AVDDV DVDDV AVDDV DVDDV DVDDV DVDDV U D0 Q0 90 U 000P 9 U L L L 0 9 U L U L 9 U L 0 9 U L R 0K R K R 0K/N R 0K/N R 0K/N R 0K/N R 0K/N DVDDV_ DVDDV_ AVDDV_ DVDDV_ DVDDV_ RSORF RRR SSFLG DVDDV_ AVDDV_ SLOK SSFLG0 RLOK

69 9 SQUMAS LÉROS Placa Principal L/0 FLASH/DDR/JAG DU V DU S DU DU W DU VSS DU DU DU Q HOLD D Serial Flash PDD HOLD#_F 9 0 U00 N/MP PDD R0 R09 POO# POO# FLASH_WP# FLASH_WP# PDD PDD NOR_S# R0 N/ R9 N/ R99 N/0K GPO_ V_FLASH DVDDV PDD_FLASH DVDDV L00 0 R0 K R0 K DVDDV PO# PO0# NOR_S#

70 0 SQUMAS LÉROS Placa Principal L/0 FLASH/DDR/JAG S/SO0 SLK SO V WP#/SO SO/SO S# RS circuit.v(v).v(9v).v L=MU System Reset# R 0K R K R9 N/K MAN_POWR PDD_MX R R _Q0 V_FLASH POO ORS# SO PDD POO# U0 R9 N/ R0 K Q0 90 R9 K U R K PDD_FLASH PDD_FLASH NOR_S# R 0K R 0K R R FLASH_WP# V_FLASH VS Q0 90 R9 K Q0 90 R 00K R 0 R 0K R 0K 0P OPRL0

71 SQUMAS LÉROS Placa Principal L/0 FLASH/DDR/JAG A0 A A A A A A A A A9 A0 A A DQU0 DQU DQU DQU DQU DQU DQU DQU DQSU /DQSU DMU DQL0 DQL DQL DQL DQL DQL DQL DQL DQSL /DQSL DML A0 A A /S /RAS /AS /W K /K K OD /RS VRFA VRFDQ ZQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS9 VSS0 N N N N N N N VSS N P P N P P R R R L R N D A A A D F F F H H G H F G M N M L J K L J K K9 K M H L A A 9 D 9 F H H9 9 D D F9 G G9 D9 G K K N N9 R R9 A9 G J J M M9 P P9 9 J J9 L L9 M U0 HQGFR R 0 N/U 0 U K/% R DDRV DDRV DDRV K/% R R K/% DDRV 0 R K/% _A _RS# _OD _K LK0# LK0 _W# _AS# _RAS# _S# _A _A _A0 RDQM0 RDQS0# RDQS0 RDQ RDQ RDQ RDQ RDQ RDQ RDQ RDQ0 RDQM RDQS# RDQS RDQ RDQ RDQ RDQ RDQ RDQ0 RDQ9 RDQ _A _A _A0 _A9 _A _A _A _A _A _A _A _A _A0 RVRF RVRF ZQ

72 SQUMAS LÉROS Placa Principal L/0 FLASH/DDR/JAG SDA SL W V VSS /N /N 0/N ADDRSS "A0" SYSM PROM W- _SL _DA DV OSDA0 OSL0 R K R K N/R R _A _A R0 0 _A0 _A0 R 0 _S# _S# R 0 _OD _OD R 0 0 R R0 0 R0 R0 _A _A _A _A _K _A0 _A _A _A _A _A _A _A0 _A _A9 _RS# 0 R _A _RAS# _AS# _W# _A _A _A _A _K _A0 _A _A _A _A _A _A _A _RAS# _AS# _W# R 0 0 R0 0 R9 0 U0 MMN 0 0P 09 0P 0 DVDDV DVDDV R0 K LK0 LK0# RLK0 RLK0# _A _RS# _A9 _A0 R 0K R0 0K Q00 90 GPO_

73 SQUMAS LÉROS Placa Principal L/0 VAL? RS&MU RU DGAL AS0 AMP AUDO_PWR AUDO_PWR R9 N/ R99 N/ L0 U V R 0K R9 K R 0K L0 D0 LL D0 LL 0 U R K R 0K Q 90 R K Q0 90 R0 K V V DVDDV AMP_V R 0 R9 R R R R R 00P 00P 00P L R R 09 U U 0 U V V R 0K R K Q09 90 R K L 00P AMP_RS OPRL AMLK ALK ALRLK AOSDAA0 AOLRK AOLK AOMLK ASDAA0 MU

74 SQUMAS LÉROS Placa Principal L/0 P_A P_A OU_ PVDD_ PVDD_ S_ S_ PVDD_ PVDD_ OU_ P_D P_D OU_D PVDD_D PVDD_D S_D GVDD_OU VRG A DVSS DVDD SS RS SL SDA SDN SLK LRLK PDN VR_DG DVSSO OS_RS MLK FAUL AVDD PLL_FLP PLL_FLM AVSS N O_ADJ SSMR GVDD_OU S_A PVDD_A PVDD_A OU_A VR_ANA R+ R- L+ L- SPK_R+/SU+ SPK_R-/SU- SPK_L+ P0 P0 L+ 0 U 0 U U L0 R- R+ L- R 0 VR_DG R0 0 0U V U U 0 0.0U 9 0.0U 0.0U 0.0U V U 9 N/0P N/0P N/0P N/0P L0 UH L0 UH L0 UH L00 UH R R 0 0.U 0.0U 0.0U 00P U0 AS0 R 00P R9 N/ R9 N/ R N/ 9 0P R K AVSS V R0 K R9 K L AVSS 0.0U R R R AMP_V AMP_V R 9 00P 0 0.0U AMP_V AMP_V L 0 0.0U 0 0.U R9 R R R 0P ASDAA0 ALK ALRLK VR_DG AMLK OSDA0 OSL0 AMP_RS MU SPK_L-

75 SQUMAS LÉROS Placa Principal L/0 Y0 Y Z Y Y V VSS A A0 YA Y0A ZA YA YA VDD R9 K R K R9 K R K 9 0 U00 HF0 R N/ R N/ R R 0 N/U V N/U V 0 U M99 U VGA_R_N MUX_LA R K R R AN_R0 0P R K R9 9 0P 9 U 90 U R K R K R0 K R R K R R 0K +V Q0 90 +V R K K R0 R9 0K +V Q0 90 OPRL MUX_L OPRL AN0_L_AAD AN0_R_AAD AN_L0 AN_L0 MUX_LA MUX_L AN_R0 YPPR_R_N SAR_R_N VGA_L_N YPPR_L_N SAR_L_N SDAV_L_N SDAV_R_N

76 SQUMAS LÉROS Placa Principal L/0 headphone out LOS O 0 LOS O 0 NONND=H ONND=L 00P 0 00P PHON_MU R 0K HP_R P00_ PHON_R U 00 P 0 P 0 R0 0 R U ARO 00 00U V ALO R00 K R00 K R0 K R0 K 00 00U V 99 00U V R0 R R90 HP_V R00 K Q P R00 K 009 0P 0 U U U 9 R00 K Q00 90 Q00 90 R00 K R009 K 00 U 00 U Q P R00 K Q00 90 Q00 90 R09 K R0 K R0 K R0 K 0 U Q00 90 R0 K R0 K R0 K P Q00 90 R00 K Q00 90 Q0 90 Q0 90 L 0 L 0 V_ R0 R R00 R R00 R R9 N/ PHON_R P00 PHON_R PHON_L R9 N/ L 0UH L 0UH R9 0K R99 0K PHON_R PHON_L PHON_L PHON_R 0K R K R HP_V HP_V DVDDV R K R K R K R K Q 90 N/0.0U N/0.0U 00P 0 00P PHON_MU GPO_ HP_V