Scheduling Divisible Loads on Heterogeneous Desktop Systems with Limited Memory
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- Luiz Gustavo Alencastre Cabreira
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1 Scheduling Divisible Loads on Heterogeneous Desktop Systems with Limited Memory Aleksandar Ilić and Leonel Sousa INESC-ID/ IST, TU Lisbon, Portugal 9 th Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms - HeteroPar, Bordeaux, 2011
2 Motivation COMMODITY COMPUTERS = HETEROGENEOUS SYSTEMS Multi-core General-Purpose Processors (CPUS) Many-core Graphic Processing Units (GPUS) Special accelerators, co-processors, FPGAs, => SIGNIFICANT COMPUTING POWER Not yet completely explored for COLLABORATIVE COMPUTING TO USE THE AVAILABLE RESOURCES AND IMPROVE PERFORMANCE/WATT HETEROGENEITY MAKES PROBLEMS MUCH MORE COMPLEX! Scheduling, performance modeling and load balancing Different programming models, languages and implementations 2
3 Outline DISCRETELY DIVISIBLE LOAD (DDL) PROCESSING HETEROGENEOUS (CPU+GPU) DESKTOP SYSTEMS PERFORMANCE MODELING AND DDL SCHEDULING ALGORITHM CASE STUDY: 2D FFT Batch Execution CONCLUSIONS AND FUTURE WORK 3
4 Discretely Divisible Load Processing DISCRETELY DIVISIBLE LOAD (DDL) APPLICATIONS Computations divisible into pieces of arbitrary sizes (integers) Fractions independently processed in parallel with no precedence constraints APPLICABLE TO A WIDE RANGE OF SCIENTIFIC PROBLEMS Linear algebra, digital signal and image processing, database applications STATE OF THE ART DDL APPROACHES IN HETEROGENEOUS DISTRIBUTED COMPUTING Assume symmetric bandwidth and an one-port model for communication links Limited memory: only the size of input load is considered; the exceeding load is simply redistributed among the nodes with available memory Unrealistic: Computation/communication time is a linear/affine function of the #chunks 4
5 Heterogeneous Desktop Systems HETEROGENEOUS STAR NETWORK (MASTER-WORKER) MULTI- CPU (Master) Global execution controller; access the whole global memory All cores employed for execution INTERCONNECTION BUSES Bidirectional full-duplex asymmetric communication Different concurrency levels Potential execution bottleneck DEVICES (Distant workers) Different architectures and programming models Computation performed using local memories CONT ROL INTERCONNECTION BUSES DEVICE #N DEVICE #2 GPU #1 CPU #1... CACHE #2 #N 5
6 Proposed Algorithm Outline (1) 2-STEP DIVISIBLE LOAD SCHEDULING CPU CONT ROL #1... CACHE #2 #N INTERCONNECTION BUSES DEVICE #N DEVICE #2 GPU #1 6
7 Proposed Algorithm Outline (2) 2-STEP DIVISIBLE LOAD SCHEDULING STEP 1 SYSTEM-LEVEL LOAD BALANCING How many load units to send to each device? CONT ROL CPU #1... CACHE #2 #N INTERCONNECTION BUSES DEVICE #N DEVICE #2 GPU #1 7
8 Proposed Algorithm Outline (3) 2-STEP DIVISIBLE LOAD SCHEDULING STEP 1 SYSTEM-LEVEL LOAD BALANCING How many load units to send to each device? CONT ROL CPU #1... CACHE #2 #N INTERCONNECTION BUSES DEVICE #N DEVICE #2 GPU #1 8
9 Proposed Algorithm Outline (4) 2-STEP DIVISIBLE LOAD SCHEDULING STEP 1 SYSTEM-LEVEL LOAD BALANCING How many load units to send to each device? STEP 2 DEVICE-LEVEL LOAD SCHEDULING How to sub-partition the device load to: Reduce delays when distributing and retrieving Overlap computation and communication Efficiently use the bidirectional asymmetric bandwidth of buses Respect the amount of supported concurrency CONT ROL CPU #1... CACHE #2 #N INTERCONNECTION BUSES DEVICE #N DEVICE #2 GPU #1 Fit into device limited memory 9
10 Proposed Algorithm Outline (5) 2-STEP DIVISIBLE LOAD SCHEDULING STEP 1 SYSTEM-LEVEL LOAD BALANCING How many load units to send to each device? STEP 2 DEVICE-LEVEL LOAD SCHEDULING How to sub-partition the device load to: Reduce delays when distributing and retrieving Overlap computation and communication Efficiently use the bidirectional asymmetric bandwidth of buses Respect the amount of supported concurrency CONT ROL CPU #1... CACHE #2 #N INTERCONNECTION BUSES DEVICE #N DEVICE #2 GPU #1 Fit into device limited memory 10
11 Proposed Algorithm Outline (6) 2-STEP DIVISIBLE LOAD SCHEDULING STEP 1 SYSTEM-LEVEL LOAD BALANCING How many load units to send to each device? STEP 2 DEVICE-LEVEL LOAD SCHEDULING How to sub-partition the device load to: Reduce delays when distributing and retrieving Overlap computation and communication Efficiently use the bidirectional asymmetric bandwidth of buses Respect the amount of supported concurrency CONT ROL CPU #1... CACHE #2 #N INTERCONNECTION BUSES DEVICE #N DEVICE #2 GPU #1 Fit into device limited memory 11
12 Performance Modeling FUNCTIONAL PERFORMANCE MODELS Continuous performance functions (#chunks/time) Built from the real application execution No assumptions being made to ease modeling! COMPUTATION PERFORMANCE MODELS - For each master core and distant worker FULL-DUPLEX COMMUNICATION BANDWIDTH -, Bidirectional and asymmetric for each link ψ τ ψ w TOTAL PERFORMANCE OF EACH DEVICE σ ι σ o Including computation and communication CONT ROL INTERCONNECTION BUSES DEVICE #N DEVICE #2 GPU #1 CPU #1... CACHE #2 #N 12
13 Determination of Load Fractions (1) STEP 1 SYSTEM-LEVEL LOAD BALANCING β 1 β 2 β 3 β 4 The total load N is partitioned between devices The optimal distribution lies on a straight line passing through the origin of coordinate system and intersecting communication-aware total performance curves ( ), such that*: β 1 ψ τ1 (β 1 ) = = N ψ τ β k ψ τk (β k ) = = n β j =N j=1 β n ψ τn (β n ) CONT ROL INTERCONNECTION BUSES DEVICE #N DEVICE #2 GPU #1 CPU #1... CACHE #2 #N *Lastovetsky, A., and R. Reddy, "Distributed Data Partitioning for Heterogeneous Processors Based on Partial Estimation of their Functional Performance Models", HeteroPar 2009, LNCS, vol. 6043, Springer, pp ,
14 Determination of Load Fractions (2) STEP 2 DEVICE-LEVEL SCHEDULING Per-device distributions β j are allowed to exceed the device memory limits, b j Device-level multi-installment processing with multi-distributions Γ k γ k,l β 1 sub-distributions with sub-load fractions Γ 1 Γ 2 Γ 3 14
15 Determination of Load Fractions (3) STEP 2 DEVICE-LEVEL SCHEDULING Per-device distributions β j are allowed to exceed the device memory limits, b j Device-level multi-installment processing with multi-distributions Γ k γ k,l β 1 sub-distributions with sub-load fractions Γ 1 Γ 2 Γ 3 15
16 Determination of Load Fractions (4) STEP 2 DEVICE-LEVEL SCHEDULING Per-device distributions β j are allowed to exceed the device memory limits, b j Device-level multi-installment processing with multi-distributions Γ k γ k,l β 1 sub-distributions with sub-load fractions Γ 1 γ 1,1 γ 1,2 γ 1,4 Γ 2 Γ 3 γ 3,1 γ 3,2 γ 3,4 16
17 Determination of Load Fractions (5) - Limited Memory - STEP 2 DEVICE-LEVEL SCHEDULING Per-device distributions β j are allowed to exceed the device memory limits, b j Device-level multi-installment processing with multi-distributions Γ k γ k,l sub-distributions with sub-load fractions Application memory requirements are modeled with three functions of load size: Input memory requirements, µ ι (x) Output memory requirements, µ o (x) Execution memory requirements, µ w (x, P ) Different implementations of the same problem might have different memory requirements! Each Γ k sub-distribution may request the whole amount of memory, such that: Γk (µ ι (γ k,l )+µ w (γ k,l,p j )+µ o (γ k,l )) b j l=1 Γ Γ k γ k,l = β j k=1 l=1 17
18 Determination of Load Fractions (6) - Computation/Communication Overlapping - STEP 2 DEVICE-LEVEL SCHEDULING Γ k γ k,l For each sub-distribution, sizes are carefully chosen to allow as best as possible overlapping of computation and communication between subsequent sub-fractions Execution Time (no overlap) Γ 1 γ 1,1 γ 1,2 γ 1,4 Γ 2 Γ 3 γ 3,1 γ 3,2 γ 3,4 18
19 Determination of Load Fractions (7) - Computation/Communication Overlapping - STEP 2 DEVICE-LEVEL SCHEDULING Γ k γ k,l For each sub-distribution, sizes are carefully chosen to allow as best as possible overlapping of computation and communication between subsequent sub-fractions Execution Time (overlapped) Γ 1 γ 1,1 γ 1,2 γ 1,4 Γ 2 Γ 3 γ 3,1 γ 3,2 γ 3,4 Execution Time (no overlap) 19
20 Determination of Load Fractions (8) - Computation/Communication Overlapping - STEP 2 DEVICE-LEVEL SCHEDULING Γ k γ k,l For each sub-distribution, sizes are carefully chosen to allow as best as possible overlapping of computation and communication between subsequent sub-fractions Execution Time (overlapped) Γ 1 γ 1,1 γ 1,2 γ 1,4 Γ 2 GAIN Γ 3 γ 3,1 γ 3,2 γ 3,4 Execution Time (no overlap) Gain size depends on how well the chunks are overlapped! 20
21 Determination of Load Fractions (9) - Computation/Communication Overlapping - STEP 2 DEVICE-LEVEL SCHEDULING Γ k γ k,l For each sub-distribution, sizes are carefully chosen to allow as best as possible overlapping of computation and communication between subsequent sub-fractions The decisions are made according to the amount of overlapping concurrency supported by the device: γ k1 t ι (γ k1 ) t w (γ k1 ) t o (γ k1 ) γ k2 t ι (γ k2 ) t w (γ k2 ) t o (γ k2 ) t ι (γ k4 ) t w (γ k4 ) γ k3 t ι (γ k3 ) t w (γ k3 ) t o (γ k3 )... (a) Overlap of a single communication with computation at the time γ k1 t ι (γ k1 ) t w (γ k1 ) t o (γ k1 ) γ k2 t ι (γ k2 ) t w (γ k2 ) t o (γ k2 ) t ι (γ k4 ) t w (γ k4 ) γ k3 t ι (γ k3 ) t w (γ k3 ) t o (γ k3 )... (b) Complete concurrency between communication and computation 21
22 Determination of Load Fractions (10) - DEVICE-LEVEL SCHEDULING ALGORITHM - STEP 2 DEVICE-LEVEL SCHEDULING ALGORITHM* γ k1 t ι (γ k1 ) t w (γ k1 ) t o (γ k1 ) γ k2 t ι (γ k2 ) t w (γ k2 ) t o (γ k2 ) t ι (γ k4 ) t w (γ k4 ) γ k3 t ι (γ k3 ) t w (γ k3 ) t o (γ k3 )... According to the performance models for device computation ( ) and bidirectional asymmetric full-duplex communication links ( σ ι, σ o ) ψ w * Ilić, A., and Sousa, L., Algorithm For Divisible Load Scheduling on Heterogeneous Systems with Realistic Performance Models, Tech. rep., INESC-ID (May 2011) 22
23 Determination of Load Fractions (11) - DEVICE-LEVEL SCHEDULING ALGORITHM - STEP 2 DEVICE-LEVEL SCHEDULING ALGORITHM* γ k1 t ι (γ k1 ) t w (γ k1 ) t o (γ k1 ) γ k2 t ι (γ k2 ) t w (γ k2 ) t o (γ k2 ) t ι (γ k4 ) t w (γ k4 ) γ k3 t ι (γ k3 ) t w (γ k3 ) t o (γ k3 )... According to the performance models for device computation ( ) and bidirectional asymmetric full-duplex communication links ( σ ι, σ o ) Step 2-I. Determination of the initial optimal distribution with three load fractions. ψ w * Ilić, A., and Sousa, L., Algorithm For Divisible Load Scheduling on Heterogeneous Systems with Realistic Performance Models, Tech. rep., INESC-ID (May 2011) 23
24 Determination of Load Fractions (12) - DEVICE-LEVEL SCHEDULING ALGORITHM - STEP 2 DEVICE-LEVEL SCHEDULING ALGORITHM* γ k1 t ι (γ k1 ) t w (γ k1 ) t o (γ k1 ) γ k2 t ι (γ k2 ) t w (γ k2 ) t o (γ k2 ) t ι (γ k4 ) t w (γ k4 ) γ k3 t ι (γ k3 ) t w (γ k3 ) t o (γ k3 )... According to the performance models for device computation ( ) and bidirectional asymmetric full-duplex communication links ( σ ι, σ o ) Step 2-I. Determination of the initial optimal distribution with three load fractions. Step 2-II. Generate additional three-fraction distributions. ψ w * Ilić, A., and Sousa, L., Algorithm For Divisible Load Scheduling on Heterogeneous Systems with Realistic Performance Models, Tech. rep., INESC-ID (May 2011) 24
25 Determination of Load Fractions (13) - DEVICE-LEVEL SCHEDULING ALGORITHM - STEP 2 DEVICE-LEVEL SCHEDULING ALGORITHM* γ k1 t ι (γ k1 ) t w (γ k1 ) t o (γ k1 ) γ k2 t ι (γ k2 ) t w (γ k2 ) t o (γ k2 ) t ι (γ k4 ) t w (γ k4 ) γ k3 t ι (γ k3 ) t w (γ k3 ) t o (γ k3 )... According to the performance models for device computation ( ) and bidirectional asymmetric full-duplex communication links ( σ ι, σ o ) Step 2-I. Determination of the initial optimal distribution with three load fractions. Step 2-II. Generate additional three-fraction distributions. Step 2-III. Insert additional load fractions into existing sub-distributions (iterative). ψ w * Ilić, A., and Sousa, L., Algorithm For Divisible Load Scheduling on Heterogeneous Systems with Realistic Performance Models, Tech. rep., INESC-ID (May 2011) 25
26 Determination of Load Fractions (14) - DEVICE-LEVEL SCHEDULING ALGORITHM - STEP 2 DEVICE-LEVEL SCHEDULING ALGORITHM* γ k1 t ι (γ k1 ) t w (γ k1 ) t o (γ k1 ) γ k2 t ι (γ k2 ) t w (γ k2 ) t o (γ k2 ) t ι (γ k4 ) t w (γ k4 ) γ k3 t ι (γ k3 ) t w (γ k3 ) t o (γ k3 )... According to the performance models for device computation ( ) and bidirectional asymmetric full-duplex communication links ( σ ι, σ o ) Step 2-I. Determination of the initial optimal distribution with three load fractions. Step 2-II. Generate additional three-fraction distributions. Step 2-III. Insert additional load fractions into existing sub-distributions (iterative). Step 2-IV. Generate new sub-distributions by restarting. ψ w * Ilić, A., and Sousa, L., Algorithm For Divisible Load Scheduling on Heterogeneous Systems with Realistic Performance Models, Tech. rep., INESC-ID (May 2011) 26
27 Determination of Load Fractions (15) - DEVICE-LEVEL SCHEDULING ALGORITHM - STEP 2 DEVICE-LEVEL SCHEDULING ALGORITHM* γ k1 t ι (γ k1 ) t w (γ k1 ) t o (γ k1 ) γ k2 t ι (γ k2 ) t w (γ k2 ) t o (γ k2 ) t ι (γ k4 ) t w (γ k4 ) γ k3 t ι (γ k3 ) t w (γ k3 ) t o (γ k3 )... According to the performance models for device computation ( ) and bidirectional asymmetric full-duplex communication links ( σ ι, σ o ) Step 2-I. Determination of the initial optimal distribution with three load fractions. Step 2-II. Generate additional three-fraction distributions. Step 2-III. Insert additional load fractions into existing sub-distributions (iterative). Step 2-IV. Generate new sub-distributions by restarting. Step 2-V. Expand all sub-distributions. ψ w * Ilić, A., and Sousa, L., Algorithm For Divisible Load Scheduling on Heterogeneous Systems with Realistic Performance Models, Tech. rep., INESC-ID (May 2011) 27
28 Determination of Load Fractions (16) - DEVICE-LEVEL SCHEDULING ALGORITHM - STEP 2 DEVICE-LEVEL SCHEDULING ALGORITHM* γ k1 t ι (γ k1 ) t w (γ k1 ) t o (γ k1 ) γ k2 t ι (γ k2 ) t w (γ k2 ) t o (γ k2 ) t ι (γ k4 ) t w (γ k4 ) γ k3 t ι (γ k3 ) t w (γ k3 ) t o (γ k3 )... According to the performance models for device computation ( ) and bidirectional asymmetric full-duplex communication links ( σ ι, σ o ) Step 2-I. Determination of the initial optimal distribution with three load fractions. Step 2-II. Generate additional three-fraction distributions. Step 2-III. Insert additional load fractions into existing sub-distributions (iterative). Step 2-IV. Generate new sub-distributions by restarting. Step 2-V. Expand all sub-distributions. Step 2-VI. Select the distribution with maximum relative performance. ψ w * Ilić, A., and Sousa, L., Algorithm For Divisible Load Scheduling on Heterogeneous Systems with Realistic Performance Models, Tech. rep., INESC-ID (May 2011) 28
29 Case Study: 2D FFT Batch DOUBLE FLOATING POINT COMPLEX 2D FFT BATCH EXECUTION Size: 256 times ; divisible in the first dimension The optimal vendor-provided FFT implementations are used NVIDIA s CUFFT 3.2 for the GPU and Intel MKL 10.3 for the CPU Experimental Setup HETEROGENEOUS CPU+GPU DESKTOP SYSTEM ITERATIVE PROCEDURE FOR ONLINE PERFORMANCE MODELING PERFORMANCE ESTIMATION of all heterogeneous devices DURING THE EXECUTION No prior knowledge on the performance of an application is available on any of the devices INITIALLY, the load is distributed among devices using FACTORING-BY-TWO STRATEGY Limited Memory: Factoring-by-two partitioning of the largest loads into new sub-distributions until satisfying the memory limitations IN EACH FOLLOWING ITERATION, the load is distributed using the PRESENTED APPROACH CPU Intel Core 2 Quad GPU nvidia GeForce 285GTX Speed/Core (GHz) Global Memory (MB)
30 Case Study: 2D FFT Batch ITERATION 1: FACTORING-BY-TWO STRATEGY 320" β 1 = 64 β 2 = 64 β 3 = 64 β 4 = 64 GPU" Core"1" Core"2" Core"3" Rela/ve"Performance" 240" 160" 80" Γ= { {32,16,8,4,2,1,1} } 0" 0" 64" 128" 192" 256" Number"of"chunks" 30
31 Case Study: 2D FFT Batch ITERATION 1: FACTORING-BY-TWO STRATEGY 320" β 1 = 64 β 2 = 64 β 3 = 64 β 4 = 64 GPU" Core"1" Core"2" Core"3" Rela/ve"Performance" 240" 160" 80" Γ= { {32,16,8,4,2,1,1} } 8 points for GPU modeling (7 actual, 1 accuracy) 0" 0" 64" 128" 192" 256" Number"of"chunks" 31
32 Case Study: 2D FFT Batch ITERATION 1: PROPOSED ALGORITHM Rela/ve"Performance" 320" 240" 160" 80" β 1 = 181 β 2 = 29 β 3 = 23 β 4 = 23 GPU" Core"1" Core"2" Core"3" Γ= { {8,14,18,20,9,1} {8,14,8,20,21,21,9} } 0" 0" 64" 128" 192" 256" Number"of"chunks" 32
33 Case Study: 2D FFT Batch ITERATION 2: PERFORMANCE MODELS 320" β 1 = 181 β 2 = 29 β 3 = 23 β 4 = 23 GPU" Core"1" Core"2" Core"3" Rela/ve"Performance" 240" 160" 80" Γ 1 Γ 2 Γ 0" 0" 64" 128" 192" 256" Number"of"chunks" 33
34 Case Study: 2D FFT Batch ITERATION 2: MODELING EFFICIENCY 320" β 1 = 181 β 2 = 29 β 3 = 23 β 4 = 23 GPU" Core"1" Core"2" Core"3" Rela/ve"Performance" 240" 160" 80" Γ 1 Γ 2 Γ 23 points for GPU modeling (14 actual, 9 accuracy) 0" 0" 64" 128" 192" 256" Number"of"chunks" 34
35 Case Study: 2D FFT Batch ITERATION 2: ALGORITHM EFFICIENCY 320" β 1 = 181 β 2 = 29 β 3 = 23 β 4 = 23 GPU" Core"1" Core"2" Core"3" Rela/ve"Performance" 240" 160" 80" 4.6x CUFFT 23 points for GPU modeling (14 actual, 9 accuracy) 0" 0" 64" 128" 192" 256" Number"of"chunks" 35
36 Case Study: 2D FFT Batch ITERATION 3 320" β 1 = 199 β 2 = 23 β 3 = 17 β 4 = 17 GPU" Core"1" Core"2" Core"3" Rela/ve"Performance" 240" 160" 80" 4.5x CUFFT 37 points for GPU modeling (22 actual, 15 accuracy) 0" 0" 64" 128" 192" 256" Number"of"chunks" 36
37 Case Study: 2D FFT Batch ITERATION 4 320" β 1 = 205 β 2 = 21 β 3 = 15 β 4 = 15 GPU" Core"1" Core"2" Core"3" Rela/ve"Performance" 240" 160" 80" 4.3x CUFFT 53 points for GPU modeling (25 actual, 28 accuracy) 0" 0" 64" 128" 192" 256" Number"of"chunks" 37
38 Case Study: 2D FFT Batch COMPARISON WITH STATE OF THE ART APPROACHES 320" Proposed" [10]" [6]" Rela/ve"Performance" 240" 160" 80" #Iterations to converge Proposed [10] [6] Load Balancing YES NO NO #Points for GPU Modeling #Points per iteration 53 (4 iters) 10 (10 iters) 8 (8 iters) " 0" 64" 128" 192" 256" Number"of"chunks" 4.3x faster in determining the steady-state distribution (complete algorithm time) comparing to the approach from [10], and 3.2x faster comparing to [6] (ping-pong state) Load balanced distribution achieves 2x better performance comparing to the steadystate distribution from [10], and 2.2x better performance than [6] [6] Galindo, I., Almeida, F., Badıa-Contelles, J.M.: Dynamic load balancing on dedicated heterogeneous systems. In: PVM/ MPI. pp (2008) [10] Lastovetsky, A., Reddy, R.: Data partitioning with a functional performance model of heterogeneous processors. Int. J. High Perform. Comput. Appl. 21, (2007) 38
39 Conclusions DYNAMIC LOAD BALANCING OBTAINED IN 4 ITERATIONS AND 4.1 SECONDS (IN TOTAL) TRADITIONAL APPROACHES FOR PERFORMANCE MODELING Approximate the performance using number of points equal to the number of iterations In this case, 4 POINTS in total for GPU performance modeling (4 iterations) PRESENTED DDL SCHEDULING APPROACH Models the GPU performance using 53 POINTS, in this case ~13x more than with traditional modeling Load balancing solution is 2x faster than the current state of the art approach IN THIS CASE, OBTAINED GPU PERFORMANCE IS AT LEAST 4.3X BETTER THAN THE OPTIMAL CUFFT EXECUTION 39
40 Questions? Thank you 40
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