Unifying Stream Based and Reconfigurable Computing to Design Application Accelerators

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1 Unifying Stream Based and Reconfigurable Computing to Design Application Accelerators Bruno Francisco, Frederico Pratas and Leonel Sousa VLSI-SoC 2010 Madrid, Spain Wednesday, September 29th

2 Motivation Co-processing hardware can be a very efficient solution to accelerate certain types of applications However, mapping algorithms into hardware is not straightforward Relatively easier to program according to the stream-based computing model (many streambased algorithms have been proposed for different applications, e.g. for running on GPUs) 2

3 Proposed Work The stream-based description is suitable as an approximation to hardware description: decouples computation from memory accesses and communication exposes the parallelism available in the application Stream-based description can be used as an intermediate step: besides being easier and faster to implement it also provides the HW designer with early-stage programmable prototyping platforms Algorithm 3

4 Proposed Work Stream-based approach gives us the computational core Full system integration using a standard systematic approach The design of the ALU is obtained from the stream-based implementation The Datapath Control Unit is modified according to the data flow The size of the Storage Unit is modified according to the data used in algorithm Accelerator SU CPU ALU DCU 4

5 Outline Overview Stream-based Computing Hardware Design Case Study MrBayes Overview Stream-based Parallelization From Stream-based to Reconfigurable Hardware Experimental Setup and Results Conclusions and Future Work 5

6 Overview: Stream-based Computation A data stream is a sequence of data items. In stream computing one or more kernels, comprising several operations in sequence, are applied to a single or multiple input data streams to produce an output data stream. Independent communication and computation. Input data Streams Kernel Processor Output data streams 6

7 Overview: Hardware Design Efficient solutions but complex design Customizable Differently optimized for each application Adaptable/Reconfigurable Different applications can be dynamically loaded Hard to: automatically map algorithms into hardware Debug, regarding software solutions Input data streams Input Memory Buffer Custom Kernel Output Memory Buffer Output data streams FPGA Control Logic 7

8 Overview: Hardware Design Efficient solutions but complex design Customizable Differently optimized for each application Adaptable/Reconfigurable Different applications can be dynamically loaded Hard to: automatically map algorithms into hardware We try to overcome these difficulties: stream-based computing (GPUs) hardware accelerators Debug, regarding software solutions Input data streams Input Memory Buffer Custom Kernel Output Memory Buffer Output data streams FPGA Control Logic 8

9 Overall Procedure Prototyping platform The stream-based algorithm is programmed in CUDA The GPU is used for optimization and debugging The algorithm is ported to VHDL with a minimum effort and integrated in the overall standard system Stream-based Algorithm GPU programed with CUDA VHDL Design 9

10 Case Study: MrBayes The whole procedure starts with a target algorithm MrBayes is a bioinformatics application that performs Bayesian inference of evolutionary (phylogenetic) trees. Profiling showed that >85% of the program execution is spent in the Phylogenetic Likelihood Functions (PLF) Main data structures: Q A A C G T r 0... r n Conditional Likelihood vector m elements C G T A Adenine C Cytosine G Guanine T Thymine A C G T r 0... r n 10

11 Stream-based Parallelization Primitive kernel Stream-Based Parallelization cl - Right/Left child 4 Substitution Matrix Q(R/L) Thread 3 Thread Thread 1 Results Thread R/L inner products More details about the CUDA implementation and the algorithm parallelization can be found at F. Pratas, et. al, Fine-grain Parallelism using Multi-core, Cell/BE, and GPU Systems: Accelerating the Phylogenetic Likelihood Function, In ICPP 09, Vienna, Austria. 11

12 From Stream-based to Reconfigurable Hardware Optimizations Right/Left child Substitution Matrix Q(R/L) S0 S1 S2 S3 S4 S5 S6 S7 cll 0 pl 0 cll 2 cll 3 cll 0 pl 0 cll 1 pl 1 pl 2 + cll 2 pl 2 + pl 3 + cll 3 pl Left + Right cll 1 pl 1 Parallel operations Hardware Reusing Deeper pipelining S0 S1 S2 S3 S4 S5 clr 3 pr 3 cll 3 pl 3 clr 2 pr 2 cll 2 pl 2 clr 1 pr 1 cll 1 pl 1 clr 0 pr 0 cll 0 pl 0 + Left/Right ALU MU Accelerator Core Resultant More details about the optimization procedure can be found at F. Pratas, et. al, Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study, In International Workshop SAMOS 09, Samos, Greece. 12

13 Building the Processing Unit Right/Left child Substitution Matrix Q(R/L)!" #" $%& $%: '& ': $%: )5-5 (&" +,%-.'%./ /47 MU =><5?%/ (88/ /47 ALU Resultant )*" *;<-0;% +,%-.'%./ /47 13

14 Building the Processing Unit Right/Left child Substitution Matrix Q(R/L)!" #" $%& $%: '& ': $%: )5-5 (&" +,%-.'%./ /47 MU =><5?%/ (88/ /47 ALU Resultant )*" *;<-0;% +,%-.'%./ /47 14

15 Building the Processing Unit Right/Left child Substitution Matrix Q(R/L)!" #" $%& $%: '& ': $%: )5-5 (&" +,%-.'%./ /47 MU =><5?%/ (88/ /47 ALU Resultant )*" *;<-0;% +,%-.'%./ /47 15

16 Building the Processing Unit Right/Left child Substitution Matrix Q(R/L)!" #" $%& $%: '& ': $%: )5-5 (&" +,%-.'%./ /47 MU =><5?%/ (88/ /47 ALU Resultant )*" *;<-0;% +,%-.'%./ /47 16

17 Building the Processing Unit Right/Left child Substitution Matrix Q(R/L)!" #" $%& $%: '& ': $%: )5-5 (&" +,%-.'%./ /47 MU =><5?%/ (88/ /47 ALU Resultant )*" *;<-0;% +,%-.'%./ /47 17

18 Building the Processing Unit Right/Left child Substitution Matrix Q(R/L)!" #" $%& $%: '& ': $%: )5-5 (&" +,%-.'%./ /47 MU =><5?%/ (88/ /47 ALU Resultant )*" *;<-0;% +,%-.'%./ /47 18

19 Overall System Integration Propose a generic structure prepared for deployment and replication of the PU We provide a simple software interface to use on the CPU side Because the stream-based approach decouples computation from communication we could analyze different communication scenarios between the CPU and the FPGA ):5: $==-011 %"& $==-011 9*:;<0 #%& '5:-5>?0105 "& 89*:;<0 )%& '& ):5: "& 89*:;<0 )%& '& ):5: %.*5-.< $(& %.*5-.< $(&!"#$ *+,-./0112*3+4*251+6"&7 19

20 Experimental Setup Device Type Board Bus type Slices #BRAMs #DSPs Virtex 4 (C4VS35) Real Annapolis Wildcard 4 PCMCIA 15, Virtex 4 (C4F60) Real Avnet ilinx V4F PCIe 8x 25, Virtex 4 (C4VS55) Hypothetic n/a PCIe 16x 24, Virtex 5 (C5VF200T) Hypothetic n/a RocketIO 30, The Stream-based implementation was programmed with CUDA API v3.1 An Intel 1.86GHz was used as host system and as reference system. The GPU results were obtained with an NVIDIA GT285@1.48GHz The hardware was described in VHDL, synthesized with Synplify Premier D and the Place&Route was obtained with ilinx ISE MrBayes version with input datasets obtained from Seq-Gen. 20

21 Experimental Results Place&Route Device Area (Slices) Frequency BRAMs DSPs PUs C4VS35 89% 181 MHz 35% 75% 12 C4F60 40% 177 MHz 24% 75% 8 C4VS55 99% 176 MHz 46% 65% 28 C5VF200T 53% 181 MHz 42% 100% 64 Average DSP occupancy of 79% The frequency is not significantly affected The throughput scales with the #PUs implemented The latency is approximately constant because the parallelism is the only factor being modified across different topologies. 21

22 Experimental Results 1456"7/8" #!!" +!" *!" )!" (!" '!" &!" %!" $!" #!"!" $$'')",-&./,%'",-&0,(!"",-&./,''",-'.0,$!!1" 213$*'" SpeedUp relative to the baseline xc4vsx35 xc4fx60 xc4vsx55 xc5vfx200t GT285 19:;<"=6>?6<"@56" A955B?4-;@9?"@56" CDE"@56" C4VS35 is the most affected device due to the low bandwidth of the PCMCIA bus (20MB/s) C5VF200T shows a speedup of the accelerated kernel of 223x, however it drops to 18x with the overheads of communication Overall, we could obtain an improvement of up to 1.5x. We obtain comparable results to the GPU using 27% of PUs and 12% of the frequency. Total SpeedUp Kernel+Communication SpeedUp ALU SpeedUp 22

23 Conclusions and Future Work We proposed a systematic approach to build the overall system. The stream-based implementation is used as an intermediate step, naturally leading to scalable hardware architectures. The results show that the solution is efficient, both in terms of performance and power consumption, even not being a completely custom solution. However, the limited bandwidth of the bus has a huge impact. In the future we plan to test the proposed design using a SoC solution continue this work by applying our approach to different algorithms develop software tools based on the proposed systematic approaches to assist in hardware design. 23

24 Questions? Acknowledgements technology from seed Dr. Alexandros Stamatakis Dr. Pedro Trancoso 9/28/10 24

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